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Designing with the PlanAhead Analysis and Design Tool

Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.

Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.

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Who Should Attend

FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.

At-A-Glance	Schedule
Course No: FPGA11000-ILT Course Duration: 16 HR Price: USD $1,200 or 12 Xilinx Training Credits Level: Intermediate Prerequisites Essentials of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE® software flow Designing for Performance recommended Software Tools Xilinx ISE Design Suite: Logic or System Edition 11.1	Nothing currently scheduled. Please contact us for customized classes. Tel: (702) 736-4116 • Fax: (865) 251-9771

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COURSE OUTLINE

Day 1

PlanAhead Tool Benefits and Features Overview
Lab 1: Getting Started with the PlanAhead Tool
I/O Pin and Clock Planning
Lab 2: Assigning I/O Pins
RTL Development and Analysis
Lab 3: RTL Development and Analysis
Implementing a Design
Lab 4: Implementing with the PlanAhead Tool

Day 2

Design Analysis
Lab 5: Design Analysis

Floorplanning Techniques
Lab 6: Floorplanning
Debugging with the ChipScope Tool
Lab 7: Debugging with the ChipScope Tool
Project Navigator Integration with the PlanAhead Tool
Lab 8: Using the PlanAhead Tool with Project Navigator
Course Summary

LAB DESCRIPTION

Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.

Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.
Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.
Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).
Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.
Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software.
Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.
Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope^™ Pro cores and tools.
Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAheadtool integrated within the ISE software Project Navigator environment.