Designing with the PlanAhead Analysis and Design Tool
Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool.Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.
Note: The hands-on labs provided within this course are identical tothe tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and a demonstration.
Project Navigator Integration with the PlanAhead Tool
Lab 8: Using the PlanAhead Tool with Project Navigator
Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.
Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.
Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.
Lab 3:RTL Development and Analysis– Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).
Lab 4:Implementing with the PlanAhead Tool– Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.
Lab 5: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software.
Lab 6: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.
Lab 7: Debugging with the ChipScope Tool – Provides an introduction to using the PlanAhead tool for debugging designs with the ChipScope™ Pro cores and tools.
Lab 8: Using the PlanAhead Tool with Project Navigator – Illustrates some of the capabilities and benefits of using the PlanAheadtool integrated within the ISE software Project Navigator environment.