Advanced Verilog

This comprehensive course focuses on advanced simulation techniques that among other things, leverage the enhanced Verilog 2001 File IO capabilities. The course covers writing user-defined subprograms ( tasks and functions ) as part of creating a robust verification strategy. The course also demonstrates important proprietary tool features and concepts, such as Code Coverage from MTI’s ModelSim product, and Xilinx™s own ISIM tool. FPGA device level optimization is also discussed, from the standpoint of Verilog RTL coding, including using and simulating Xilinx CoreGen modules. In addition, back-annotated timing simulation techniques are demonstrated. This course will enhance testing and verification skills for existing Verilog designers while improving quality-of-results for Xilinx FPGA based applications...DOWNLOAD XILINX ADVANCED VERILOG COURSE DETAIL



At-A-Glance

Schedule

  • Course No:  LANG22000-8-ILT
  • Course Duration:  2 Days
  • Price:  USD $1,400
    or 14 Xilinx Training Credits
  • Level: Intermediate to Advanced
  • Prerequisites

    > Basic digital design knowledge
    > Intro to Verilog

  • Software Tools

    > Xilinx ISE™ 8.1i
    > ModelSim® 6.2 Simulator
    > Synplicity Synplify Pro

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

Day 1
> Verilog tasks and functions
> ModelSim/ISIM Overview
> Advanced ModelSim/ISIM features
> Lab 1: Create subprograms for simulation
> Advanced Test bench Concepts
> Verilog 2001 Enhanced File I/O capability
> Lab 2: Read input stimulus from external file

Day 2
> Writing, storing and comparing outputs
> Lab 3: Write simulation results to file
> Strategies for self-checking test bench
> Lab 4: Perform automated comparison, reporting
> Using Xilinx CoreGen modules
> Advanced FPGA synthesis, timing constraints
> Code Coverage with ModelSim
> Lab 5: Simulating with Code Coverage

LAB DESCRIPTION

The labs for this course offer a practical hands-on opportunity to create robust and re-usable testbenches. Each exercise is carefully constructed to permit discovery while exploring options and tradeoffs. In addition to the comprehensive step-by-step instructions, the lab documentation also provides additional insight regarding the tool, procedures or best-case practices.


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