Xilinx® Authorized Training Provider Courses > DSP Design > DSP Implementation Techniques for FPGAs
DSP Implementation Techniques for FPGAs

This course shows you how to take advantage of the features available in the Xilinx FPGA architecture, including the Virtex.-4 FPGA, and describes how DSP algorithms can be implemented efficiently. The techniques also demonstrate which decisions at the system level have the greatest impact on the implementation process and product costs.

...DOWNLOAD DSP Implementation Techniques for Xilinx FPGAs COURSE DETAIL



Who Should Attend

Engineers and designers who have an interest in developing products that use digital signal processing



At-A-Glance

Schedule

  • Course No:  DSP20000-ILT
  • Course Duration:  3 Days
  • Price:  USD $2,100
    or 21 Xilinx Training Credits
  • Level: Advanced
  • Prerequisites

    A fundamental understanding of digital signal processing theory, including an understanding of the following principles:

    > Sample rates
    > Finite Impulse Response (FIR) and Infinite Impluse Response (IIR) filters
    > Oscillators and mixers
    > Fast Fourier Transform (FFT) algorithm

  • Software Tools
  • October 5-7, 2010
    Orange County, CA

    Doubletree - Orange County Airport

    7 Hutton Centre Dr.

    Santa Ana, California,

    United States 92707-5794


    Tel: 1-714-751-2400   Fax: 1-714-662-7935

     


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COURSE OUTLINE

Day 1
> On the Same Wavelength
    - Basic terminology and acronyms used in DSP design
    - Sample rates and bit widths used in DAP applications
    - DSP building blocks and processing requirements
> Some Bits About Numbers
    - Numbering formats, range, and percision
    - Mathematical operations using a variety of formats
> Tuning the Receiver
   - Structure and Resources of Xilinx Devices
   - Estimating DSP building block sizes

Day 2
> Tuning the Receiver (continued)
   - Implementing the multiplication function
   - Bit-width impact on system-level decisions
> Memories are Made of This
    - Block Versus distributed memory
    - SRL 16 E and the delay function
    - Memory aspect ratios and their manipulation
> Selective Filters
    - FIR filter specifications and implementation
    - Selecting a technique for a given specification
    - Effects of halfband and interpolated filters

Day 3
> One Filter Does Not Make a System
    - Options to be considered with multiple channels
    - Interpolation and decimation
    - Rate changing and its effect on FIR filter choice
    - Filtering algorithms that exploit device architecture
    - Importance of connectivity versus isolated functions
> Do Not Block the Datapath
    - Numeric controlled oscillators and mixers
    - Strategies for FFT implementation
    - Achieving bandwidth requirements of the FFT
    - Using the FPGA as an efficient co-processor

LAB DESCRIPTION


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