Xilinx® Authorized Training Provider Courses > PCI Design > Designing a LogiCORE PCI System
Designing a LogiCORE PCI System

Learn the tips and tricks of PCI designs in this two-day course. This course provides an introduction to basic PCI concepts and architecture and intensive training on designing with the Xilinx PCI core. Emphasizes and illustration are to how PCI transactions take place and gives you an overview of Xilinx PCI solutions. You will learn the basics of Xilinx PCI cores including PCI 64/66 and PCI 32. You will also learn design concepts and basic verification strategies for creating a PCI system design. The labs cover basic transaction analysis with the ModelSimä simulator and the general design flow, from core to verification, with ISE 6.3i...DOWNLOAD XILINX DESIGNING A LOGICORE PCI SYSTEM COURSE DETAIL



At-A-Glance

Schedule

  • Course No:  PCI28000-ILT
  • Course Duration:  2 Days
  • Price:  USD $1,400
    or 14 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites

    > Some knowledge of PCI
    > Working experience with digital design
    > Basic knowledge of Verilog or VHDL
    > Experience with either Xilinx Alliance Series™ or Foundation™ ISE software tools

  • Software Tools

    > ISE 6.3i
    > ModelSim 5.8c

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

Day 1
> Introduction
> PCI Local Bus Architecture
> PCI Signals
> Basic Bus Operations: Transactions, Decoding, and Wait States
> Basic Bus Operations: Target, Parity, and Arbitration
> PCI Addressing and Bus Commands
> PCI Configuration > 64-Bit and 66-MHz PCI
> PCI Timing
> The LogiCORE PCI Solution
> Xilinx 32/33 and 64/66 LogiCORE PCI Day 2
> User Application Interface for Target
> User Application Interface for Initiator
> Other User Interface Signals
> Practical Design of PCI Agents
> Xilinx PCI 64-Bit and 66 MHz
> Implementing the LogiCORE PCI
> Device-Specific Considerations

LAB DESCRIPTION

Lab 1: Analyzing PCI Bus Transactions. This lab demonstrates typical PCI bus transactions and the signals associated with each type of bus transaction. The relationship between various signals is identified. Various settings are changed and the behaviors are analyzed after each change is made.

Lab 2: Synthesis and Implementation Using XST. Demonstration of the Xilinx PCI design flow, from synthesis to an implementation targeted for a device that supports Xilinx PCI using ISE 6.3i software. The lab uses the example “Pingâ€ï¿½ design (included with the PCI Core) to target a Virtex-II® FPGA. Similar steps can be followed for other device families.


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