Xilinx® Authorized Training Provider Courses > DSP Design > DSP Design Using System Generator
DSP Design Using System Generator

This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.

 

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Who Should Attend

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design

 



At-A-Glance

Schedule

  • Course No:  DSP11000-ILT
  • Course Duration:  16:00 HR
  • Price:  USD $1,400
    or 14 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites

    • Experience with the MATLAB and Simulink software
    • Basic understanding of sampling theory

     

  • Software Tools

    Software Tools

    • Xilinx ISE® Design Suite: System Edition 11.3
    • MATLAB with Simulink software R2008b or R2009a

  • September 21-22, 2010
    Orange County, CA

    Doubletree - Orange County Airport

    7 Hutton Centre Dr.

    Santa Ana, California,

    United States 92707-5794


    Tel: 1-714-751-2400   Fax: 1-714-662-7935

     


  • November 22-23, 2010
    San Diego, CA

    Torrey Villas Conference Center

    11100 Vista Sorrento Parkway

    San Diego, CA 92130-8616

     


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COURSE OUTLINE

Day 1

Introduction to System Generator

Simulink Software Basics

Lab 1: Using the Simulink Software

Basic Xilinx Design Capture

Lab 2: Getting Started with Xilinx System Generator

Signal Routing

Lab 3: Signal Routing

Implementing System Control

Lab 4: Implementing System Control

 


Day 2

Multi-Rate Systems

Lab 5: Designing a MAC-Based FIR

Filter Design

Lab 6: Designing a FIR Filter Using the FIR Compiler Block

Xilinx System Generator, Project Navigator, and Platform Studio Integration

Lab 7: System Generator and Project Navigator Integration

 

 

LAB DESCRIPTION

Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.

Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.

Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.

Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.

Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.

Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.

Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.


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