This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.
Who Should Attend
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design
Introduction to System Generator
Simulink Software Basics Lab 1: Using the Simulink Software
Basic Xilinx Design Capture Lab 2: Getting Started with Xilinx System Generator
Signal Routing Lab 3: Signal Routing
Implementing System Control Lab 4: Implementing System Control
Multi-Rate Systems Lab 5: Designing a MAC-Based FIR
Filter Design Lab 6: Designing a FIR Filter Using the FIR Compiler Block
System Generator, Vivado Design Suite, Project Navigator, and XPS Integration Lab 7: System Generator and Vivado IDE Integration
Kintex-7 FPGA DSP Platforms Lab 8a. System Generator and Vivado HLS Tool Integration Lab 8 b. AXI4-Lite Interface Synthesis
Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.
Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.
Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
Lab 7: System Generator and Vivado IDE Integration – Embed System Generator models into the Vivado IDE.
Lab 8a: System Generator and Vivado HLS Tool Integration – Generate IP from a C-based design to use with System Generator.
Lab 8b: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq All Programmable SoC processor system.