Advanced ModelSim for Verilog
This informative one day course offers a balance of language and tool specific topics that can greatly improve design verification results and enhance engineering productivity. The fast-paced course covers how to fully leverage VHDL Text I/O for both reading input stimulus from, and writing simulation results to external files. It also covers ModelSim specific features such as basic scripting, automated waveform comparison and Code coverage. This class affords existing VHDL designers the opportunity to quickly apply advanced simulation techniques that immediately save time, promote consistency and yield an overall more robust design ...DOWNLOAD TSI ADVANCED MODELSIM FOR VHDL COURSE DETAIL
- Course Duration: 1 Day
- Price: USD $600
or 6 Xilinx
Intermediate to Advanced
> Basic design knowledge
> ISE™ 8.2i
> ModelSim 6.2 Simulator
> Xilinx XST™
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763
Do you want to receive news and schedule updates for this course? Subscribe to the Technically Speaking news email list
> Advanced ModelSim Features
> VHDL functions and procedures >
Intro to VHDL Text I/O
> Lab 1: Read input stimulus from external file
> Advanced VHDL Text I/O Concepts
\> Lab 2: Compare simulation results, write to file
> Using ModelSim Code Coverage Features
> Lab 3: Measure code coverage, improve scores
The labs for this course offer a practical hands-on opportunity to create robust and re-usable verification strategies. Each exercise is carefully constructed to permit discovery while exploring options and tradeoffs. In addition to the comprehensive step-by-step instructions, the lab documentation also provides additional insight regarding the tools, procedures or best-case practices.