Learn how to employ GTX serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Who Should Attend
FPGA designers and logic designers
At-A-Glance
Schedule
Course
No: RIO22000-ILT
Course Duration: 2 Days
Price: USD $1,400
or 14 Xilinx
Training Credits
Level:
Connectivity 3
Prerequisites
Verilog or VHDL experience (or the Introduction to Verilog or
the Introduction to VHDL course)
Familiarity with logic design (state machines and synchronous
design)
Basic knowledge of FPGA architecture and Xilinx
implementation tools is helpful
Familiarity with serial I/O basics and high-speed serial I/O
standards is also helpful
Software
Tools
Vivado™ System Edition 2012.3
ChipScope™ Pro software 14.3
Mentor Graphics ModelSim simulator 10.1
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763
Lab 8: System Lab or IBERT Lab Using Xilinx Boards
Transceiver Application Examples
LAB DESCRIPTION
Lab 1: 8B/10B Encoder and Decoder– Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.
Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.
Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.
Lab 5: GTX Core Generation – Use the 7 Series FPGAs Transceivers Wizard to create instantiation templates.
Lab 6: Simulation and Implementation – Instantiate the GTX transceiver component in a design, synthesize the design, and implement the design.
Lab 7: 64B/66B Encoding – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results.
Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.
