Xilinx® Authorized Training Provider Courses > Connectivity > Designing with Multi-Gigabit Serial I/O 2 Day
Designing with Multi-Gigabit Serial I/O 2 Day

 

 

COURSE DESCRIPTION

 

Learn how to employ GTX serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.



Who Should Attend

FPGA designers and logic designers



At-A-Glance

Schedule

  • Course No:  RIO22000-ILT
  • Course Duration:  2 Days
  • Price:  USD $1,400
    or 14 Xilinx Training Credits
  • Level: Connectivity 3
  • Prerequisites

    •  Verilog or VHDL experience (or the Introduction to Verilog or
      the Introduction to VHDL course)
    •  Familiarity with logic design (state machines and synchronous
      design)
    • Basic knowledge of FPGA architecture and Xilinx
      implementation tools is helpful
    •  Familiarity with serial I/O basics and high-speed serial I/O
      standards is also helpful
  • Software Tools

    •     Vivado® System Edition 2013.2
  • February 11-12, 2015
    Orange County, CA

    Orange County - TBD

    (near John Wayne Airport)


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COURSE OUTLINE

Day 1

          7 Series FPGAs Overview

          7 Series FPGAs Transceivers Overview

          7 Series FPGAs Transceivers Clocking and Resets

          8B/10B Encoder and Decoder

          Lab 1: 8B/10B Encoding and Bypass

          Commas and Deserializer Alignment

          Lab 2: Commas and Data Alignment

          RX Elastic Buffer and Clock Correction

          Lab 3: Clock Correction

Day 2

          Channel Bonding

          Lab 4: Channel Bonding
          Transceiver Wizard Overview

          Lab 5: Transceiver Core Generation

          Simulating and Implementing a Transceiver Design

          Lab 6: Transceiver Simulation and Implementation

          64B/66B Encoding and the Gearbox

          Lab 7: 64B/66B Encoding

          Transceiver Test and Debugging

          Lab 8: System Lab or IBERT Lab Using Xilinx Boards

LAB DESCRIPTION

  •           Lab 1: 8B/10B Encoder and Decoder – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
  •           Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.
  •           Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.
  •           Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.
  •          Lab 5: Transceiver Core Generation – Use the 7 Series FPGAs Transceivers Wizard to create instantiation templates.
  •          Lab 6: Simulation and Implementation – Instantiate the transceiver component in a design, simulate the design, synthesize the design, and implement the design.
  •          Lab 7: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the 7 Series FPGAs Transceivers Wizard, simulate the design, and analyze the results.
  •          Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.


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