Xilinx® Authorized Training Provider Courses > FPGA Design/Architecture > Signal Integrity and Board Design for Xilinx FPGA's
Signal Integrity and Board Design for Xilinx FPGA's

Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.




Who Should Attend

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.




  • Course No:  SI20000-ILT
  • Course Duration:  3 Days
  • Price:  USD $2,100
    or 21 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites


    •  FPGA design experience preferred (Essentials of FPGA Design
      course or equivalent)
    •  Familiarity with high-speed PCB concepts
    • Basic knowledge of digital and analog circuit design
    •  ISE® tool knowledge is helpfu
  • Software Tools

    •  Xilinx ISE Design Suite: System Edition 13.1

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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Part 1Signal Integrity
 Signal Integrity Introduction
 Transmission Lines
 IBIS Models and SI Tools
 Lab 1: Invoking HyperLynx
 Lab 2: Reflection Analysis
 Lab 3: Crosstalk Analysis
 Signal Integrity Analysis
 Power Supply Issues
 Signal Integrity Summary
Part 2 – Board Design
 Board Design Introduction
 FPGA Power Supply
 Lab 4: Power Prediction
 FPGA Configuration and PCB
 Signal Interfacing: Interfacing in General
 Signal Interfacing: FPGA-Specific Interfacing 
 Lab 5: I/O Pin Planning
 Die Architecture and Packaging
 PCB Details
 Thermal Aspects
 Lab 6: Thermal Design
 Tools for PCB Planning and Design
 Board Design Summary


 Lab 1: Invoking HyperLynx – Become familiar with signal integrity
tools. Use HyperLynx for schematic entry, modeling, and
simulation. Modify a standard IBIS model to define a driver and
then use its stackup editor to define a PCB.
 Lab 2: Reflection Analysis – Define a circuit and run various
simulations for effects of reflection.
 Lab 3: Crosstalk Analysis – Using simulation, analyze circuit
topology and PCB data for strategies to minimize crosstalk.
 Lab 4: Power Prediction – Estimate initial power requirements
using an Excel spreadsheet, then use XPower Analyzer to
accurately predict board power needs.
 Lab 5: Pin Planning – Use the PlanAhead software to identify pin
placement and implement pin assignments.
 Lab 6: Thermal Design – Determine maximum junction
temperature and calculate acceptable thermal resistanc

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