As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug.
This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.
Who Should Attend
System and logic designers who want to minimize verification and debug time
Course Duration: 2 Days
Price: USD $1,400
or 14 Xilinx
Basic language concepts for both days
Designing with VHDL or equivalent knowledge of VHDL
Designing with Verilog or equivalent knowledge of Verilog
Basic FPGA skills for Day 1
Essentials of FPGA Design
Intermediate FPGA skills for Day 2
Designing for Performance or Vivado Static Timing Analysis and Xilinx Design Constraints
ChipScope Pro Software REL strongly recommended
Xilinx ISE® Design Suite: Logic or System Edition 14.2
ChipScope Pro tool 14.2
Vivado™ System Edition 2012.2 (optional)
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763
Labs 1 and 2: Using the Inserter Tool from the PlanAhead Design Environment or Vivado Design Suite
Instantiating the Cores – CORE Generator Tool Flow
Lab 3: Using the CORE Generator Tool from the PlanAhead Design Environment
Triggering and Storage
Visualizing Data – The ChipScope Pro Analyzer Tool
Lab 4: Triggering and Visualization in the Analyzer Tool
Tips and Tricks
Lab 5: Tips and Tricks
Time for Timing
Video Demo – Area Groups for Isolation
Lab 6: FPGA Editor Support for the ChipScope Pro Tool
Remote Access (Optional)*
Lab 7: Remote Access (Optional)*
Check with your Authorized Training Provider to confirm whether this content is included with your specific class.
Labs 1 and 2: Using the Inserter Tool from the PlanAhead Design Environment or Vivado Design Suite – Insert ICON and ILA cores into an existing netlist and debug a common problem.
Lab 3: Using the CORE Generator Tool from the PlanAhead Design Environment– Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool.
Lab 4: Triggering and Visualization in the Analyzer Tool – Configure triggers and view captured data using the ChipScope Pro Analyzer tool.
Lab 5: Tips and Tricks – Keep time across multiple sample windows and sample across multiple time domains.
Lab 6: FPGA Editor Support for the ChipScope Pro Tool – Change the signals being sampled by an ILA without having to reimplement the design.
Lab 7: Remote Access – Use the ChipScope Pro Analyzer tool to configure an FPGA, set up triggering, and view the sampled data from a remote location.