Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
This course covers ISE software features such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.
For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.
Who Should Attend
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
Course Duration: 1 Day
Price: USD $600
or 6 Xilinx
Working HDL knowledge (VHDL or Verilog)
Digital design experience
Xilinx ISE Design Suite: Logic or System Edition 14.1
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763
Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool
Global Timing Constraints
Lab 4: Global Timing Constraints
Synchronous Design Techniques
Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project
Navigator and use the ISE Simulator to perform a behavioral
simulation. Implement the design using default software options
and download to a Spartan-6 FPGA SP605 evaluation board.
Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking
Wizard to customize a DCM and incorporate your clocking
resources into your design. Use the PlanAhead™ tool to assign
pin locations and implement the design using the Project
Navigator in the ISE software.
Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This
lab introduces the basics of making good I/O pin assignments
with the PlanAhead software. Use the Design Rule Checker to
follow the I/O banking rules.
Lab 4: Global Timing Constraints – Enter global timing constraints
with the Xilinx Constraints Editor. Review the Post-Map Static
Timing Report to verify that the timing constraints are realistic.
Use the Post-Place & Route Static Timing Report to determine
the delay of the longest constrained path for each timing