Designing with the Virtex-4 Family
Interested in learning how to utilize Virtex.-4 FPGA architectural resources effectively? This course focuses on understanding and utilizing several of the new and enhanced resources found in our newest device. Topics covered include an overview of the Virtex-4 FPGA; the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD); global and regional clocking techniques; memory and FIFO; and source-synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught in this course...DOWNLOAD DESIGNING WITH THE VIRTEX-4 FAMILY COURSE DETAIL
Who Should Attend
Experienced Xilinx users or those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. Students should have a solid understanding of Virtex-II, Virtex-II Pro, and Virtex-II ProX FPGA architectures, the ISE. software, timing constraints, and timing closure techniques.
- Course Duration: 2 Days
- Price: USD $1,200
or 12 Xilinx
Fundamentals of FPGA Design course
Designing for Performance course
Understanding of the Virtex-II Pro, Virtex-II Pro X FPGA architecture
Xilinx ISE 8.1i
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763
Do you want to receive news and schedule updates for this course? Subscribe to the Technically Speaking news email list
DCM Clock Management
PMCD Clock Management
Lab 1: DCM Clocking
Lab 2: Clocking Resources
Day Two Overview
I/O and Source-Synchronous Resources
Lab 3: Utilizing Source-Synchronous I/O Resources
Block RAM Memory Resources
FIFO16 Memory Resources
Lab 4: Utilizing Block RAM and FIFO16
XtremeDSP. Technology Slice
Lab 5: Utilizing XtremeDSP Technology Resources
Day Two Review
Lab 1: DCM Clocking. Designing a clock management scheme with DCMs and PMCDs.
Lab 2: Clocking Resources. Utilizing global and regional clock networks.
Lab 3: Utilizing Source-Synchronous I/O Resources. Creating a source-synchronous design interface for a network application.
Lab 4: Utilizing Block RAM and FIFO16. Utilizing new block RAM features and FIFO16-dedicated resources.
Lab 5: Utilizing XtremeDSP Technology Resources. Utilizing the DSP48 block.