Technically Speaking Course Listing | Xilinx® Authorized Training Provider | PCI Design

Designing a LogiCORE PCI Express System

Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system within the Connectivity Targeted Reference Design (TRD). With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the AXI streaming interconnect.

COURSE DESCRIPTION

Who Should Attend

Hardware designers who want to create applications using Xilinx IP cores for PCI Express
Software engineers who want to understand the deeper workings of the Xilinx LogiCORE™ PCI Express solution
System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

At-A-Glance

Schedule

Course No: PCIE28000-14-ILT
Course Duration: 2 Days
Price: USD $1,400
or 14 Xilinx Training Credits
Level: Connectivity 3
Prerequisites
- Experience with PCIe specification protocol
- Knowledge of VHDL or Verilog
- Some experience with Xilinx implementation tools
- Some experience with a simulation tool, preferably ISim
- Moderate digital design experience
Software Tools
- Xilinx ISE® Design Suite: Logic or System Edition 14.2
- ChipScope™ Pro software 14.2

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763

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COURSE OUTLINE

Day 1
Introduction to the PCIe Architecture
Review of the PCIe Protocol
PCIe and the CORE Generator™ Interface
Lab 1: Constructing the PCIe Core
Simulating a PCIe System Design
Connecting Logic to the Core – AXI Interface
Packet Formatting Details
Lab 2: Downstream Port Model Simulation

Day 2

Endpoint Application Considerations
Lab 3: Pseudo-Transactional Modeling
Application Focus: DMA
Lab 4: Design Implementation
Virtex-6 FPGA Root Port
Compliance and Debugging
Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools
Errors and Interrupts
Appendix: Mechanicals, Hot Plug, and Power
Appendix: Connecting Logic to the Core – Local Link

LAB DESCRIPTION

Lab 1: Constructing the PCIe Core – This lab familiarizes you
with all the necessary flow of the Xilinx CORE Generator™ tool
for generating a Xilinx LogiCORE Endpoint Block IP. You will
select appropriate parameters for the CORE Generator tool and
create the PCIe core used throughout the labs.
Lab 2: Downstream Port Model Simulation – This lab
demonstrates how timing and behavior of a typical link negotiation
using the ISim tool. You will observe and capture the effects of
link training and write packets to the endpoint application for later
use.
Lab 3: Pseudo-Transactional Modeling – This lab illustrates
pseudo-transactional modeling, which provides various packets to
the user design without the need to simulate the PCIe cores
themselves.

Lab 4: Design Implementation – This lab familiarizes you with all
the necessary steps and recommended settings to turn the HDL
source to a bitstream.
Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools –
This lab illustrates how to use the ChipScope™ Pro tools to
monitor the behavior of the core and the endpoint application for
proper operation