Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system within the Connectivity Targeted Reference Design (TRD). With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the AXI streaming interconnect.
Who Should Attend
Hardware designers who want to create applications using Xilinx IP cores for PCI Express
Software engineers who want to understand the deeper workings of the Xilinx LogiCORE™ PCI Express solution
System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications
Course Duration: 2 Days
Price: USD $1,400
or 14 Xilinx
Experience with PCIe specification protocol
Knowledge of VHDL or Verilog
Some experience with Xilinx implementation tools
Some experience with a simulation tool, preferably the Vivado® simulator
Moderate digital design experience
Vivado Design or System Edition 2014.3
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763
Lab 5: Debugging the PCIe Core with Vivado Logic Analyzer**
Interrupts and Error Management
Appendix: Mechanicals, Hot Plug, and Power
Appendix: 7 Series Gen3 PCIe Core Solutions
Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
Lab 2: Downstream Port Model Simulation – This lab demonstrates how timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture the effects of link training and write packets to the endpoint application for later use.
Lab 3: Pseudo-Transactional Modeling – This lab illustrates pseudo-transactional modeling, which provides various packets to the user design without the need to simulate the PCIe cores themselves.
Lab 4: Design Implementation – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream.
Lab 5: Debugging the PCIe Core with the Vivado Logic Analyzer – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and the endpoint application for proper operation.