Attending the Designing a LogiCORE PCI Express System will provide you a working knowledge of how to implement a Xilinx PCI Express® core in your applications. This course focuses on the implementation of a Xilinx PCI Express system within the Connectivity Targeted Reference Design (TRD). With this experience, you can improve your time to market with your PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid you in selecting the proper solution. This course focuses on the AXI streaming interconnect.
Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools
Errors and Interrupts
Appendix: Mechanicals, Hot Plug, and Power
Appendix: Connecting Logic to the Core – Local Link
Lab 1: Constructing the PCIe Core – This lab familiarizes you
with all the necessary flow of the Xilinx CORE Generator™ tool
for generating a Xilinx LogiCORE Endpoint Block IP. You will
select appropriate parameters for the CORE Generator tool and
create the PCIe core used throughout the labs.
Lab 2: Downstream Port Model Simulation – This lab
demonstrates how timing and behavior of a typical link negotiation
using the ISim tool. You will observe and capture the effects of
link training and write packets to the endpoint application for later
Lab 3: Pseudo-Transactional Modeling – This lab illustrates
pseudo-transactional modeling, which provides various packets to
the user design without the need to simulate the PCIe cores
Lab 4: Design Implementation – This lab familiarizes you with all
the necessary steps and recommended settings to turn the HDL
source to a bitstream.
Lab 5: Debugging the PCIe Core with the ChipScope Pro Tools –
This lab illustrates how to use the ChipScope™ Pro tools to
monitor the behavior of the core and the endpoint application for