Introduction to AccelDSP

 Learn how to synthesize an algorithm written in the language of the MATLAB® software into a design that is optimized for a Xilinx FPGA. Find out how to make coding changes in the MATLAB software that improve area and performance. Use the floating-point to fixed-point and design exploration features of the AccelDSP synthesis tool to achieve maximum results. Merge a synthesized MATLAB software block into a larger HDL design or System Generator design.

Download Detailed Course Description



Who Should Attend

Engineers seeking to develop the necessary skills for designing DSP systems using the Xilinx AccelDSP synthesis tool running with MATLAB software



At-A-Glance

Schedule

  • Course No:  DSP12000-ILT
  • Course Duration:  2 Day
  • Price:  USD $1,200
    or 12 Xilinx Training Credits
  • Level: Fundamental
  • Prerequisites
    •  Fundamental knowledge of the MATLAB software
    •   Basics of digital signal processing theor
  • Software Tools

    •  Xilinx ISE® Foundation™ 10.1 software with the ISE Simulator
    •  AccelDSP synthesis tool 10.1
    •  System Generator for DSP 10.1
    •  MATLAB R2007

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

Day 1
 Introduction to the AccelDSP Synthesis Tool and Lab
 Synthesizable MATLAB Software Design and Lab
 Quantization and Lab
 Multirate Design and Lab
 Using AccelWare Reference Designs and Lab
Day 2
 Design Exploration and Lab
 Adding Hardware Control and Lab
 Coding for Hardware Performance and Lab
 Synthesizing Complex Numbers and Lab
 Interfacing to System Hardware and Lab
 System Generator Integration and La

  •  

LAB DESCRIPTION

 Lab 1: Getting Started with the AccelDSP Synthesis Tool –
Learn the basic design flow through the AccelDSP synthesis tool.
 Lab 2: Synthesizable MATLAB Software Design – Modify a
non-synthesizable MATLAB software design so that it can be
synthesized by the AccelDSP synthesis tool.
 Lab 3: Quantization – Specify, monitor, and control bit growth in
the synthesized design.
 Lab 4: Multirate Design – Set up the design to model the effects
of decimation by 2. Create a synthesizable polyphase decimation
filter in the MATLAB software and implement the filter in a Xilinx
FPGA.
 Lab 5: Using AccelWare Reference Designs – Replace a
polyphase decimation filter with an equivalent FIRdecim
AccelWare™ reference design block.
 Lab 6: Design Exploration – Apply the design exploration
features of the AccelDSP synthesis tool to optimize a design for
area and performance.
 Lab 7: Adding Hardware Control – Modify the source of a FIR
filter to add a serial coefficients load feature.
 Lab 8: Coding for Hardware Performance – Learn coding
techniques to take advantage of even-symmetric coefficients and
drive higher performance.
 Lab 9: Synthesizing Complex Numbers – Explore the methods
available for synthesizing designs that use complex numbers.
 Lab 10: Interfacing to System Hardware – Connect the
interface signals generated in the AccelDSP synthesis tool to a
larger HDL design.
 Lab 11: System Generator Integration – Convert a MATLAB
software-based design into a System Generator b


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