Xilinx® Authorized Training Provider Courses > FPGA Design/Architecture > Designing with Ethernet MAC Controllers
Designing with Ethernet MAC Controllers

DOWNLOAD COURSE DESCRIPTION

Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements.



Who Should Attend
Engineers who would like to come up to speed on utilizing Xilinx Ethernet connectivity solutions (soft cores and hard IP)


At-A-Glance

Schedule

  • Course No:  EMAC23000-ILT
  • Course Duration:  2 Days
  • Price:  USD $1,400
    or 14 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites
    •           Essentials of FPGA Design course
    •           C programming knowledge recommended
    •           Experience with the Xilinx ISE® and Embedded Development Kit (EDK) software tools
  • Software Tools

     

    •           Xilinx ISE Design Suite: System Edition 13.3
    •           Mentor Graphics ModelSim SE 10.0b

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

Day 1

          Ethernet Basics
          Network Protocols, Ethernet Interfaces, and Hardware
          Lab 1: Analyzing Ethernet Frames
          Physical Layer
         LocalLink Interface
          Lab 2: VLAN and Jumbo Frames
          Xilinx EMAC Solutions
Day 2
          Lab 3: Implementation
          10/100 EMAC Solutions
          Lab 4: EMAC Peripheral in Loopback Mode
          TEMAC
          Lab 5: TEMAC Peripheral in Loopback Mode
          10GE MAC
          Lab 6: Analyzing 10GE MAC Frames
 

LAB DESCRIPTION

 

          Lab 1: Analyzing Ethernet Frames – Perform a functional simulation of a Tri-Mode EMAC core using either ISim or ModelSim. Identify the components of a Gigabit Ethernet frame. Observe how the core behaves when source and destination addresses are changed.
          Lab 2: VLAN and Jumbo Frames – Analyze the transmission and reception of VLAN and jumbo frames using either ISim or ModelSim. Adjust the interframe gap value and see its effect on transmission frames. View TX_STATISTICS_VECTOR and RX_STATISTICS_VECTOR and identify their contents. Study the reception of good and bad frames and their associated signals. Analyze received jumbo frames. Analyze the management interface for the configuration registers.
          Lab 3: Implementation – Generate a Tri-Mode Ethernet MAC core by using the CORE Generator™ tool. Synthesize a core by using the XST synthesis tool via a script file generated by the CORE Generator. Implement the core using a script file. Identify what is being generated and analyze the results.
          Lab 4: EMAC Peripheral in Loopback Mode – Use XPS to create a processor system. Include an AXI 10/100 EMAC peripheral in simple non-DMA mode. Program a peripheral in loopback mode.
          Lab 5: TEMAC Peripheral in Loopback Mode – Create a processor system, including a hard TEMAC instance to the project. Program a peripheral in loopback mode. Verify the design by generating and downloading a bitstream on either the SP605 or ML605 board.
          Lab 6: Analyzing 10GE MAC Frames – Perform a functional simulation of a 10-Gigabit Ethernet MAC core. Analyze RX SGMII, TX GMII, RX client data, and TX client data.


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