Designing for Performance

Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

 Download Detailed PDF Course Description

Who Should Attend

FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools.



  • Course No:  FPGA23000-14-ILT
  • Course Duration:  16:00 HR
  • Price:  USD $1,400
    or 14 Xilinx Training Credits
  • Level: FPGA 2
  • Prerequisites


    •  Essentials of FPGA Design course or equivalent knowledge of FPGA
      architecture features; the Xilinx implementation software flow and
      implementation options; reading timing reports; basic FPGA design
      techniques; global timing constraints and the Constraints Editor
    •  Intermediate HDL knowledge (VHDL or Verilog)
    •  Solid digital design background
  • Software Tools

      ISE Design Suite: Logic or System Edition 14.1

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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Day 1

          Review of Essentials of FPGA Design

          Designing with FPGA Resources

          CORE Generator Software System

          Clocking Resources

          Lab 1: Designing With FPGA Resources

          FPGA Design Techniques

          Synthesis Techniques

          Lab 2: Synthesis Techniques

Day 2

          Achieving Timing Closure

          Lab 3: Review of Global Timing Constraints

          Path-Specific Timing Constraints, Part 1

          Path-Specific Timing Constraints, Part 2

          Lab 4: Achieving Timing Closure

          Advanced Implementation Options

          Lab 5: Designing for Performance

          Lab 6: FPGA Editor Demo (optional)

          ChipScope Pro Software (optional)
       Lab 7: Chipscope Pro Software (optional)



Lab 1: Designing with FPGA Resources – Create block RAM and
clocking FPGA cores using the CORE Generator™ tool.  Instantiate
these cores and other clock resources and implement the design.
Lab 2: Synthesis Techniques – Experiment with different synthesis
options (including timing constraints, resource sharing, synthesis
optimization effort, and register balancing) and view the results.
Lab 3: Review of Global Timing Constraints – Use the Constraints
Editor to enter global timing constraints.
Lab 4: Achieving Timing Closure – Review timing reports and enter
path-specific timing constraints to fully describe your performance
Lab 5: Designing for Performance – Improve performance and
maximize results solely with implementation options and SmartXplorer.
Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a
design and add a probe to an internal net.
Lab 7: ChipScope Pro Software (optional) – Add an internal logic
analyzer to a design to perform real-time debugging

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