This custom hybrid course is a fast-paced --lab intensive curriculum that focuses on Xilinx chip-level optimization when using Synplify Pro® or Xilinx XST® for design entry.The course covers specific synthesis options that can enhance performance and results. It then covers comprehensive Xilinx timing constraints that are critical to driving the P&R tools.The course ends with using the PlanAhead® tool to manage layout, improve timing and enhance repeatability. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten development time & lower development costs.
Course Introduction Xilinx Timing ClosureDesign Overview
Synthesis Optimization with Synplify Pro Synthesis Optimization with XST Lab 1:Use Advance Synthesis Options Xilinx FPGA Clocking Resources,V6, Spartan-6 Lab 2:Create various clocking schemes Comprehensive Timing Constraints Lab 3:Create Detailed Timing Groups
Day 2
Using Xilinx Timing Analyzer Xilinx PlanAhead ( Part I) Lab 4:Getting started with PlanAhead Xilinx PlanAhead ( Part II) Lab 5:Creating Floorplans, Analyzing Results Xilinx PlanAhead ( Part III) Lab 6:Fine-tuning Floorplans Course Review
LAB DESCRIPTION
Lab 1: Advanced Synthesis Options - For either VHDL or Verilogusers, understanding key synthesis options and menu selections
Lab 2: Create Various Clocking schemes - Use the ArchitecturalWizard to create DCM or MMCM components for various clockfrequencies and distribution requirements
Lab 3:Create Detailed Timing Groups - Use the XilinxConstraints Editor to create comprehensive Timing Constraints
Lab 4:Getting Started with PlanAhead - Create projects, performinitial design analysis
