Xilinx® Authorized Training Provider Courses > FPGA Design/Architecture > Designing with the Spartan-6 and Virtex-6 Families
Designing with the Spartan-6 and Virtex-6 Families

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Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.  
Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced.

This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA.A combination of modules and labs allow for practical hands-on application of the principles taught.




Who Should Attend

For those who have taken the Essentials of FPGA Design course.



  • Course No:  S6V6-21000
  • Course Duration:  3 Days
  • Price:  USD $1,800
    or 18 Xilinx Training Credits
  • Level: 3
  • Prerequisites
  • Software Tools

     Xilinx ISE® Design Suite: Logic or System Edition 13.

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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 Day 1
 Spartan-6 FPGA Overview
 Virtex-6 FPGA Overview
 CLB Architecture
 HDL Coding Techniques
 Lab 1: CLB Resources 
 Memory Resources
 DSP Resources

Day 2
 Lab 2: DSP Resources
 Basic I/O Resources
 Spartan-6 FPGA I/O Resources
 Virtex-6 FPGA I/O Resources
 Lab 3: I/O Resources
 Basic Clocking Resources

Day 3
 Spartan-6 FPGA Clocking Resources
 Virtex-6 FPGA Clocking Resources
 Lab 4: Clocking Resources 
 Memory Controllers
 Dedicated Hardware


            Lab 1: CLB Resources – Using XST, synthesize a 32-bit
incrementer with terminal count logic and pipelining registers.
Verify that the appropriate resources were used with the RTL and
technology viewers included with XST. Use the FPGA Editor to
inspect the implemented results.
 Lab 2: DSP Resources – Using XST, synthesize and implement
a wide MACC. Device usage will be verified via the FPGA Editor.
Using the CORE Generator™ tool, construct, instantiate, and
implement a wide pipelined multiplier. Verify the results with the
FPGA Editor.
 Lab3: I/O Resources – Using the ISE tools, complete the
construction of the transmit SERDES datapath. Explore through
simulation the behavior of the various blocks. Also use the FPGA
Editor to explore the physical resources of the FPGA that are
used for construction of a high-speed interface.
 Lab 4: Clocking Resources – Using the Clocking Wizard, build
and optimize the appropriate PLL, DCM, and clock routing
resources. Also instantiate these resources into the design. After
the design is implemented, verify hardware usage

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