TSI Proprietary Training Courses > HDL > Advanced IEEE-P1800 SystemVerilog for Design and Synthesis
Advanced IEEE-P1800 SystemVerilog for Design and Synthesis

                          ** THIS COURSE REQUIRES 8 XILINX TRAINING CREDITS **

 

Logic Specific Processes Unique & Priority - full_case & parallele_case

-  The new always type blocks show design intent and help ensure construction of proper hardware designs.  The always_type blocks are discussed in detail in this section.  This section also details how unique and priority are new SystemVerilog replacements for the dangerous "Evil Twins," full_case parallel_case.

SystemVerilog FSM Design Techniques

- Six different FSM coding styles, enhanced with new SystemVerilog constructs, are detailed and compared for coding and synthesis efficiency. Multiple FSM designs are benchmarked for coding style efficiency.

Multi-clock Clock Domain Crossing (CDC) & FIFO Design Techniques Using SystemVerilog

- Very advanced design techniques from Cliff's award-winning presentations on the efficient implementation of multi-clock CDC & FIFP designs.  These materials are not specific to SystemVerilog but solutions are shown using SystemVerilog syntax (advanced techniques that all design engineers should know - the stuff you did not learn in college

 



 

 



At-A-Glance

Schedule

  • Course No:  TSI-44000
  • Course Duration:  1 Day
  • Price:  USD $650
    or 6.5 Xilinx Training Credits
  • Level:
  • Prerequisites
  • Software Tools

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

Logic Specific Processes, Unique & Priority - full_case & parallel_case

  • Logic specific processes (always_type blocks) document designer intent
  • always_comb
  • always_latch
  • always_ff
  • Added Design checks using always_type blocks
  • ALWAYS @*-vs- always_comb
  • void functions
  • always_comb & void functions
  • Combinational sensitivity
  • Design encapsulation through void functions
  • always_ff for DDR? (SystemVerilog-2009 enhancement)
  • full_case parallel_case, "the Evil Twins"
  • What is full_case?
  • unique & priority case
  • unique & priority if unique0 (SystemVerilog-2009)
  • Three examples using case modifiers
  • *LABS: simple SystemVerilog combinational and sequential logic labs
  • *Multiple small synthesis examples

SystemVerilog FSM Design Technologies

  • FSM coding goals
  • Moore & Mealy
  • Binary & Onehot
  • ASIC -vs- FPGA FSM design
  • Review proven FSM coding styles
  • One always block - avoid this
  • Two always blocks recommended
  • Three always blocks-recommended
  • Onehot case (1'b1) - recommended
  • Onehot parameters - avoid this
  • Output encoded - recommended
  • Coding & synthesis efficiency
  • Verilog-2001 FSM enhancements
  • SystemVerilog FSM enhancements
  • Advanced enumerated types
  • LABS SystemVerilog FSM design labs

Multi-clock Clock Domain Crossing (CDC) & FIFO Design Techniques using SystemVerilog

  •  Metastability
  • Mulit-clock Clock Domain Crossing (CDC) design & Synthesis strategies
  • Multi-signal CDC technologies
  • MTBF (Mean Time Before Failure)
  • Syncing before passing multiple CDC signals
  • Multiple CDC signals-consolidation
  • Multiple CDC signals-synchronization
  • Multiple CDC signals-Multi-Cycle Path (MCP) Formulation
  • Synchronizing counters
  • Gray codes
  • Gray code counters
  • CDC Design partitioning
  • CDC simulation issues
  • CDC gate-level simulation X-avoidance techniques
  • Multi-clock FIFP design techniques from Cliff's award-winning presentations

LAB DESCRIPTION


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