Advanced IEEE-P1800 SystemVerilog for Design and Synthesis
** THIS COURSE REQUIRES 8 XILINX TRAINING CREDITS **
Logic Specific Processes Unique & Priority - full_case & parallele_case
- The new always type blocks show design intent and help ensure construction of proper hardware designs. The always_type blocks are discussed in detail in this section. This section alsodetails how unique and priority are new SystemVerilog replacements for the dangerous "Evil Twins," full_case parallel_case.
SystemVerilog FSM Design Techniques
- Six different FSM coding styles, enhanced with new SystemVerilog constructs, are detailed and compared for coding and synthesis efficiency. Multiple FSM designs are benchmarked for coding style efficiency.
- Very advanced design techniques from Cliff's award-winning presentations on the efficient implementation of multi-clock CDC & FIFP designs. These materials are not specific to SystemVerilog but solutions are shown using SystemVerilog syntax (advanced techniques that all design engineers should know - the stuff you did not learn in college
Course Duration: 1 Day
Price: USD $650
or 6.5 Xilinx
Nothing currently scheduled.
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