Designing with VHDL

 

 

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course. In this three-day course, you will gain valuable hands-on experience.
Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.



Who Should Attend

Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs



At-A-Glance

Schedule

  • Course No:  LANG11000-ILT
  • Course Duration:  3 Days
  • Price:  USD $1,800
    or 18 Xilinx Training Credits
  • Level: FPGA 1
  • Prerequisites

    Basic digital design knowledge

  • Software Tools

    •        Vivado™ System Edition 2014.1

     

     

  • November 18-20, 2014
    San Diego, CA

    Xilinx Training Ctr RB

    10815 Rancho Bernardo Rd
    STE 210
    San Diego, CA 92127


  • December 2-4, 2014
    Orange County, CA

    Orange County - TBD

    (near John Wayne Airport)


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COURSE OUTLINE

  • Day 1 
  • The “Shape” of VHDL
  •  Lab 1: Using the Tools
  •  Documentation in VHDL
  •  Data Types 
  • Concurrent Operations
  •  Lab 2: Using Concurrent Statements
  •  Processes and Variables
  •  Lab 3: Designing a Simple Process
  • Day 2 
  • Introduction to Testbenches
  •  ISim Simulation Tool Basics
  •  Lab 4: Simulating a Simple Design
  •  Creating Memory
  •  Lab 5: Building a Dual-Port Memory 
  •  Finite State Machines
  •  Lab 6: Building a Moore Finite State Machine
  •  Targeting Xilinx FPGAs
  •  Lab 7: Xilinx Tool Flow
  • Day 3 
  • Loops and Conditional Elaboration
  •  Lab 8: Using Loops
  •  Attributes
  •  Functions and Procedures
  •  Packages and Libraries
  •  Lab 9: Building Your Own Package
  •  Interacting with the Simulation
  • Writing a Good Testbench
  •  Lab 10: Building a Meaningful Testbench

LAB DESCRIPTION

The labs for this course provide a practical foundation for creating 
synthesizable RTL code. All aspects of the design flow are covered in 
the labs. You will write, synthesize, simulate, and implement all the 
labs. The focus of the labs is to write code that will optimally infer 
reliable and high-performance circuits.


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