This advanced 1 day course allows existing Xilinx EDK customers to gain additional insight and personalized assistance with their application. The instructional content focuses on leveraging the dual-port capability of the BRAM to exchange data between the Embedded Processor subsystem and the FPGA fabric. This technique is equally applicable to PPC based designs as it is for MicroBlaze based designs.
This course also utilizes the opb_intc core and covers the basics of interrupt management in addition to a brief example of the profiler.
A portion of this class is structured as open discussions on general concerns and techniques and is intended as a follow-up to the EDK or Advanced EDK Implementation class
- Course Duration: 1 Day
- Price: USD $600
> Basic digital design knowledge, Verilog or VHDL
> Basic understanding of the Virtex-4 architecture
> Basic programming skills in C
> Introduction to EDK, Advanced EDK, or equivalent knowledge
> Xilinx ISE™ 8.2i
> Xilinx Platform Studio
> Xilinx XST
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763
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> Discussion of Need
> Introduction of Software Only Design
> Lab 1: Building and Profiling S/W Only Solution
> Design Review of Hardware Solution
> Connecting Hardware and Embedded System
> Lab 2: Adding the Hardware Accelerator
> Discussion of Other BRAM Uses
> Open Discussion and EDK Follow-up
The labs for this course offer a practical hands-on opportunity to become familiar with the Platform Studio and its interface with ISE. Particular care is paid to the balance between the embedded development system and ISE. Each exercise is carefully constructed to permit discovery while exploring options and tradeoffs.Important design practices for software development and synchronous design will be reinforced.
In addition to the comprehensive step-by-step instructions, the lab documentation also provides additional insight regarding the tools, procedures or best-case practices.