Xilinx® Authorized Training Provider Courses > FPGA Design/Architecture > Custom Designing with Spartan-6 & Virtex-6 Devices
Custom Designing with Spartan-6 & Virtex-6 Devices

Open to select PNW regional customers ONLY

You Must Contact your local Xilinx, Thorson or Avnet Sales Rep or FAE to register.


Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.  


Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced.


This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.





Who Should Attend




  • Course No:  Custom S6V6
  • Course Duration:  2 Days
  • Price:  USD $0
  • Level: Custom
  • Prerequisites

    Essentials of FPGA Design course

    Intermediate VHDL or Verilog knowledge


  • Software Tools

    Xilinx ISE® Design Suite: Logic or System Edition 12.1


Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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Day 1

Spartan 6 & Virtex -6 CLB Architecture

HDL Coding Techniques

Memory Resources

DSP Resources

Lab 1: DSP Resources

Basic I/O Resources

Spartan-6 FPGA I/O Resources



Day 2

Virtex-6 FPGA I/O Resources

Lab 2: I/O Resources

Basic Clocking Resources

Spartan-6 FPGA Clocking Resources

Virtex-6 FPGA Clocking Resources

Lab 3: Clocking Resources

Memory Controllers

Lab 4: Memory Controllers



Lab 1: DSP Resources – Using XST, synthesize and implement a wide MACC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate, and implement a wide pipelined multiplier. Verify the results with the FPGA Editor.

Lab2: I/O Resources – Using the ISE tools, complete the construction of the transmit SERDES datapath. Explore through simulation the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the FPGA that are used for construction of a high-speed interface.

Lab 3: Clocking Resources Using the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.

Lab 4: Memory Controllers – Using the Memory Interface Generator, synthesize and implement a DDR3 memory controller utilizing the dedicated Spartan-6 FPGA Memory Controller Block (MCB). Download the design onto a demo board and use the ChipScope™ Pro tool to analyze the behavior of the controller.

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