Technically Speaking Course Listing | Xilinx® Authorized Training Provider | FPGA Design/Architecture

Comprehensive Xilinx Design - PART 1

This unique 4 day course covers every topic that a Xilinx FPGA
designer needs to know. This custom hybrid course combines
key sections from the FPGA Essentials, Design for
Performance, Advanced FPGA Implementation and PlanAhead
classes into a single broad based learning experience. This is
the only opportunity to cover all these topics in one training
event. The class is fast-paced and lab intensive, but each
attendee will understand both the basics, as well as the
advanced Xilinx FPGA features and capabilities. Depending on
your existing skill level, you may opt the full four days, or
separate two day(s) portions of the class. The course covers
specific synthesis options that can enhance performance and
results. It then covers comprehensive Xilinx timing constraints
that are critical to driving the P&R tools. The course ends with
using the PlanAhead® tool to manage layout, improve timing
and enhance repeatability. This course can help you fit your
design into a smaller FPGA or a lower speed grade for reducing
system costs. In addition, by mastering the tools and the design
methodologies presented in this course, you will be able to
create your design faster & lower your development costs.

Who Should Attend

All existing and potential Xilinx FPGA designers. This class is structured to meet a wide range of needs.

At-A-Glance	Schedule
Course No: TSI_12300-12-ILT Course Duration: 2 Days Price: USD $1,400 or 14 Xilinx Training Credits Level: Prerequisites Essentials of FPGA Design course or equivalent knowledge of Software Tools ISE Design Suite: Logic or System Edition 12.1 This course focuses on Spartan-6 and Virtex-6 architecture	Nothing currently scheduled. Please contact us for customized classes. Tel: 303.444.7884 • Fax: 866.402.0763

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COURSE OUTLINE

Day 1 Basic Tool Flow, Clocks, & Constraints

Course Introduction

Xilinx Tool Flow, Report Files

Global Timing Constraints

Lab 1: Write Global Constraints

Designing with FPGA Resources

V6 & S6 Clocking Resources

Lab 2: Create various clocking schemes

Day 2 Cores, FPGA Centric Design & Synthesis

Using Xilinx Timing Analyzer

FPGA Design Techniques

XST & Synplify Pro optimization techniques

Using CoreGen, Simulating Cores

Lab 3: Create module with CoreGen

Advanced Synthesis Techniques

Lab 4: Apply Synthesis Options

Day 3 Adv Timing Constraints, Design Preservation

Timing Closure

Group Specific Timing Constraints

Multicycle & False Paths

Lab 5: Create Detailed Timing Groups

Partitions and SmartGuide

Introduction to PlanAhead, features and capabilities

Lab 6: Create PlanAhead project, basic navigation

Day 4 PlanAhead, Floorplanning, Debugging

Specifying I/O Constraints

PlanAhead, features for design analysis

Lab 7: Use PlanAhead to evaluate timing, P&R results

Advanced Floorplanning techniques

Lab 8: Creating Floorplans,

Export IP for reuse, block based design

Lab 9: Create RPMs, export for reuse

ChipScope Pro Overview, Debuggin

LAB DESCRIPTION