Comprehensive Xilinx Design (4 Days)


This unique 4 day course covers every topic that a Xilinx FPGA designer needs to know.  This custom hybrid course combines key sections from the FPGA Essentials, Design for Performance, Advanced FPGA Implementation and PlanAhead classes into a single broad based learning experience.  This is the only opportunity to cover all these topics in one training event.  The class is fast-paced and lab intensive, but each attendee  will understand both the basics, as well as the advanced Xilinx FPGA features and capabilities.   Depending on your existing skill level, you may opt the full four days, or separate two day(s) portions of the class.  The course covers specific synthesis options that can enhance performance and results. It then covers comprehensive Xilinx timing constraints that are critical to driving the P&R tools.  The course ends with using the PlanAhead®  tool to manage layout, improve timing and enhance repeatability.  This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster & lower your development costs.

Who Should Attend

All existing and potential Xilinx FPGA designers.  This class is structured to meet a wide range of needs.    



  • Course No:  TSI_12300-4-ILT
  • Course Duration:  4 Days
  • Price:  USD $2,800
    or 28 Xilinx Training Credits
  • Level: FPGA 1-3
  • Prerequisites


  • Software Tools

    • ISE Design Suite: Logic or System Edition 12.1


    • This course focuses on Spartan-6 and Virtex-6 architectures  

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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Day 1

Timing Closure Overview w/HDL Design Entry
Xilinx Tool Flow Report Files
Global Timing Constraints
Designing w/FPGA resources
CORE Generator
Clocking Resources

Day 2

FPGA Design Techniques
Synthesis Techniques
Timing Closure
Path Specific Timing Constraints (Part 1)
Path Specific Timing Constraints (Part 2)
Advanced Implementation Options

Day 3

Advanced IO Timing
Floorplanning & Effective Layout
FPGA Editor

Day 4

PlanAhead Tool, features and benefits
I/O Pin planning
Placing Dedicated Resources
Creating and using Pblocks
Design Preservation w/Partitions
4 Day Course review Q & A


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