Xilinx® Authorized Training Provider Courses > FPGA Design/Architecture > Essentials of FPGA Design- Evening Edition
Essentials of FPGA Design- Evening Edition

 PLEASE NOTE:  This course is conducted in the evening from approx 6:00pm - 8:00pm

The 2 evening sessions will consist of 6 topics and 2 labs:

 

Basic FPGA Architecture

Vivado IDE Tool Overview

Vivado IDE Implementation and Static Timing Analysis

Lab: Vivado Synthesis and Implementation -  Synthesize and analyze the design with the schematic viewer, review XDC timing constraints and run basic timing analysis  using the check_timing and report_clock utilization reports. Implement the design and  analyze some timing critical paths with the Schematic Viewer. Download the bitstream to the demo board.

 

Clocking Resources

Lab:  Designing with FPGA Resources: Use the Xilinx Clocking Wizard to configure a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals to global clock networks

Basic Timing Constraints (XDC)

Synchronous Design Constraints

 



Who Should Attend

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs



At-A-Glance

Schedule

  • Course No:  ESS1300 - Evening
  • Course Duration:  4 - 6 hours
  • Price:  USD $500
    or 5 Xilinx Training Credits
  • Level:
  • Prerequisites

    Working HDL knowledge (VHDL or Verilog)

    Digital design experience

  • Software Tools

    Vivado 2012.4

    Hardware :

    • Architecture: 7 Series FPGA
    • Demo Board:   Kintex 7 FPGA KC705 board

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

 The 2 evening sessions will consist of 6 topics and 2 labs:

 

  • Basic FPGA Architecture

  • Vivado IDE Tool Overview

  • Vivado IDE Implementation and Static Timing Analysis

  • Lab: Vivado Synthesis and Implementation -  Synthesize and analyze the design with the schematic viewer, review XDC timing constraints and run basic timing analysis  using the check_timing and report_clock utilization reports. Implement the design and  analyze some timing critical paths with the Schematic Viewer. Download the bitstream to the demo board.

 

  • Clocking Resources

  • Lab:  Designing with FPGA Resources: Use the Xilinx Clocking Wizard to configure a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals to global clock networks

  • Basic Timing Constraints (XDC)

  • Synchronous Design Constraints

LAB DESCRIPTION


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