Xilinx® Authorized Training Provider Courses > FPGA Design/Architecture > Optimization & Debugging Using PlanAhead & Chipscope Pro
Optimization & Debugging Using PlanAhead & Chipscope Pro


Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.

Meanwhile, as FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug.

This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.

Who Should Attend

System and logic designers who want to minimize verification and debug time. Also FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.



  • Course No:  TSI44000 12-ILT
  • Course Duration:  16:00 HR
  • Price:  USD $1,200
    or 12 Xilinx Training Credits
  • Level: FPGA 2
  • Prerequisites
    Basic language concepts for both days
    Designing with VHDL or Verilog equivalent knowledge
    Basic FPGA skills for Day 1
    o    Essentials of FPGA Design
    ChipScope Pro Software REL strongly recommended
    Software Tools
    Xilinx ISE® Design Suite 13.1,ChipScope Pro 13.1, PlanAhead
    Demo board: Spartan-6 FPGA SP605 board*
  • Software Tools

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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Day 1
·         How the ChipScope Pro Tool Works
·         Inserting the Cores – Inserter Flows: Core Inserter and the PlanAhead Software
·         Lab 1: Using the CORE Generator Tool from Project Navigator, Triggering and Storage
·         Visualizing Data – The ChipScope Pro Analyzer Tool
·         Scripting
·         Lab 2: Using the IBERT core, demo by Xilinx FAE
·         Lab 3: Triggering and Visualization in the Analyzer Tool
·         Tips & Tricks
·         Lab 4: Tips & Tricks
Day 2
·         PlanAhead Software Review
·         Lab 5: PlanAhead Software Review
·         Placing Dedicated Resources
·         Lab 6: Placing Dedicated Resources
·         Introduction to Pblocks
·         Floorplanning Techniques
·         Lab 7: Design Analysis and Floorplanning for Performance
·         Design Preservation with Partitions
·         Lab 8: Leveraging Design Preservation with Predictable Results


 Lab Descriptions ( time permitting )

  •  Lab 1:Using the CORE Generator Tool from Project Navigator – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool
  •  Lab 2: Using the ChipScopePro IBERT debug core, Hands on demo by Don Matson, Xilinx FAE
  •  Lab 3:Triggering and Visualization in the Analyzer Tool – Configure triggers and view captured data using the ChipScope Pro Analyzer tool.
  •  Lab 4:Tips and Tricks – Keep time across multiple sample windows; sample across multiple time domains; and implement a complex custom (unconventional) trigger.
  •   Lab 5: PlanAhead Software Review – Illustrates the steps you take to import source HDL files into the PlanAhead tool and synthesize, implement, and analyze the results. Also introduces the PlanAhead tool environment and views.
  •   Lab 6: Placing Dedicated Resources – Introduces the methods for assigning location constraints to dedicated hardware resources. Demonstrates how to assign dedicated clocking resources, work with multi-function I/O pins, and complete a SSN noise analysis.
  •  Lab 7: Design Analysis and Floorplanning for Performance – Introduces the pre- and post-implementation design analysis features of the PlanAhead software. Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs.
  •  Lab 8: Leveraging Design Preservation for Predictable Results – Introduces the use of partitions to maintain successful implementation results.

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