Xilinx Critical Design Series: Timing Matters!
.jpg) Can you properly constrain a high-speed source synchronous DDR interface? Can you read a Xilinx Timing Analyzer Report to center your capture clock edge? If you’re using a 3rd party HDL design entry tool, —i.e. Synplify Pro™, should you place timing constraints in that tool, the Xilinx UCF, or both?
Attend this one day focused learning event and get the FPGA design and problem solving techniques that you need now! Technically Speaking, Inc., the Xilinx ATP for the Western USA Region is pleased to announce the first in a series of single day, topic intensive seminars, the Xilinx Critical Design series™.
Each event focuses on a particular aspect of the Xilinx FPGA design optimization challenge, the first tackling the ever-present challenge of FPGA Timing Closure. Get practical skills and knowledge that could potentially save weeks of individual effort. Each event is a combination of lecture, expert demonstration, and active audience participation. Join us for a unique and concise learning experience!
DOWNLOAD XILINX CRITICAL DESIGN SERIES DESCRIPTION
|
At-A-Glance |
Schedule |
- Course
No: XCD-1000
- Course Duration:
- Price: USD $300
or 3 Xilinx
Training Credits
- Level:
Intermediate
-
Prerequisites
- Software
Tools
|
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763
|
Do you want to receive news and schedule updates for this course? Subscribe to the Technically Speaking news email list
|
COURSE OUTLINE
|
8:30
|
Continental Breakfast
|
|
9 am
|
Global Timing Constraints
|
|
|
Anatomy of a Timing Report
|
|
|
Achieving Timing Closure (demo)
|
|
|
Timing Analyzer Options (demo)
|
|
12 pm
|
Lunch ( provided )
|
|
|
Creating Timing Groups
|
|
|
Path Specific Timing Constraints
|
|
|
Advanced I/O Timing (demo)
System & Source Synchronous
|
|
4 pm
|
Q&A End of event
|
LAB DESCRIPTION
|
|
