Technically Speaking Course Listing | Xilinx® Authorized Training Provider | FPGA Design/Architecture

Advanced FPGA Implementation

Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools.

This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE tools and the Spartan®-6 and Virtex®-6 FPGAs.

Who Should Attend

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

At-A-Glance	Schedule
Course No: FPGA33000-14-ILT Course Duration: 2 Days Price: USD $1,400 or 14 Xilinx Training Credits Level: FPGA 4 Prerequisites Essentials of FPGA Design Designing for Performance Intermediate knowledge of Verilog or VHDL is strongly recommended At least six months of design experience with Xilinx tools and FPGA Software Tools Xilinx ISE Design Suite: Logic or System Edition 14.1	Nothing currently scheduled. Please contact us for customized classes. Tel: 303.444.7884 • Fax: 866.402.0763

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COURSE OUTLINE

Introduction

Lab 1: Timing Closure REVIEW
UCF Editing
Lab 2: UCF Editing
Advanced I/O Timing
Lab 3: Advanced I/O Timing
Tcl Scripting
Lab 4: Tcl Scripting
Floorplanning an Effective Layout
Lab 5: Floorplanning
Design Preservation Techniques
Lab 6: Design Preservation
FPGA Editor: Viewing and Editing a Routed Design
Lab 7: Advanced FPGA Editor

LAB DESCRIPTION

Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.

Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.

Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.

Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.

Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.

Lab 6: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.