Accelerated Design w/PlanAhead Analysis and Design Tool
Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.
This one day “Accelerated” class fully covers the key software features, offering hardware designers a rich learning experience in a concise format.
Note: The hands-on labs provided within this course are identical tothe tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.
DOWNLOAD COURSE DESCRIPTION
Who Should Attend
FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.
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At-A-Glance |
Schedule |
- Course
No: TSI-ACC-PA-13-ILT
- Course Duration: 1 Day
- Price: USD $700
or 7 Xilinx
Training Credits
- Level:
FPGA 3
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Prerequisites
Essentials of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE®software flow
Designing for Performance recommended
- Software
Tools
Xilinx ISE Design Suite: Logic or System Edition 13.1
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Nothing currently scheduled.
Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763
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COURSE OUTLINE
Day 1
PlanAhead Tool Benefits and Features
Overview I/O Pin and Clock Planning
Lab 1: Assigning I/O Pins
RTL Development and Analysis
mplementing a Design
LUNCH
Lab 2: Implementing with the PlanAhead Tool
Design Analysis
Lab 3: Design Analysis
Floorplanning Techniques
Lab 4: Floorplanning
Course Summary
LAB DESCRIPTION
Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.
Lab 1: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.
Lab 2: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.
Lab 3: Design Analysis – Introduces the pre- and post-implementation design analysis features of the PlanAhead software.
Lab 4: Floorplanning – Provides an introduction to some of the capabilities and benefits of using the PlanAhead tool for designing high-end FPGAs. |
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