Testbenchs & Timing VHDL Text I/O, Timing Constraints & PA
This unique 1 day course is a fast-paced learning experience that focuses on using VHDL Text I/O to build robust, automated and self-checking VHDL testbenches. Specifically, the course covers how to integrate Assertion statements that simplify design verification, while reading and writing to external files.
The course then covers Xilinx FPGA chip-level optimization using the complete range of timing constraints and the PlanAhead tool to verify compliance.
Attending this course will help you create more efficient and optimal testbenches and Xilinx FPGA designs.
* This course focuses on the Spartan-6 and Virtex-6 architectures.
DOWNLOAD COURSE DESCRIPTION
Who Should Attend
Xilinx designers using IEEE-1076 VHDL to target Virtex-4, 5 & 6 devices and or the Spartan-6 FPGA family
|
At-A-Glance |
Schedule |
- Course
No: TSI_11250-13-ILT
- Course Duration: 1 day
- Price: USD $700
or 7 Xilinx
Training Credits
- Level:
VHDL3 & FPGA2
-
Prerequisites
Basic VHDL coding knowledge
Basic Xilinx Tool and Technology awareness
Essentials of FPGA Design ( 1 day class or REL )
- Software
Tools
Xilinx ISE™ 13.1i
Xilinx PlanAhead 13.1i
|
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763
|
Do you want to receive news and schedule updates for this course? Subscribe to the Technically Speaking news email list
|
COURSE OUTLINE
Day 1
VHDL Subprogram Overview
Using Text I/O to Read Input Data
Lab 1: Read input stimulus for simulation
Using Assertions to Automate Verification
Writing to External Files, User Defined Log Files
Lab 2: Perform automated comparison, write results to file
Xilinx Global FPGA Timing Constraints
Lab 3: Use constraint Editor to define timing constraints
Xilinx Group, Multicyle and False Path Constraints
Lab 4: Use PlanAhead to verify Timing Results
LAB DESCRIPTION
· Lab 1: Read Input Stimulus from External File -
Use VHDL Text I/O to define and read contents of external file
and apply directly to UUT, or for real-time comparison.
· Lab 2: Perform Automated Comparison, Write Out Results
Use VHDL Assertion statements andText I/O to read in expected simulation results, compare to actual and write results to user define log file.
· Lab 3: Use Constraint Editor to define Global Constraints
Define Xilinx global timing constraints for each clock domain using OFFSET IN, PERIOD and OFFSET OUT constraints
· Lab 4: Use PlanAhead to Verify Timing Results
Compare Timimng constraints and post P&R results within the PlanAhead tool environment. |
