How to Design a High Speed Memory Interface
COURSE DESCRIPTION
This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debug using Xilinx 7 series FPGAs.
Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.
The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR, and QDRII+. Labs are available for DDR3 on the Kintex™-7 FPGA KC705 board.
Who Should Attend
FPGA designers and logic designers
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At-A-Glance |
Schedule |
- Course
No: MEM21000-ILT (v1.0)
- Course Duration: 2 Days
- Price: USD $1,400
or 14 Xilinx
Training Credits
- Level:
Connectivity 3
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Prerequisites
- VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
- Familiarity with logic design: state machines and synchronous design
- Very helpful to have:
- Basic knowledge of FPGA architecture
- Familiarity with Xilinx implementation tools
- Nice to have:
- Familiarity with I/O basics
- Familiarity with high-speed I/O standards
- Software
Tools
- Vivado System Edition 2012.3
- Mentor HyperLynx SI
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COURSE OUTLINE
Day 1
- Course Introduction
- 7 Series FPGAs Overview
- Memory Devices Overview
- 7 Series Memory Interface Resources
- Memory Controller Details and Signals
- MIG Design Generation
- Lab 1: MIG Core Generation
Day 2
- Memory Design Simulation
- Lab 2: MIG Design Simulation
- Memory Design Implementation
- Lab 3: MIG Design Implementation
- Memory Interface Test and Debugging
- Lab 4: MIG Design Debugging
- Memory Interface Board-Level Design
LAB DESCRIPTION
- Lab 1: MIG Core Generation – Create a DDR3 memory controller using the Memory Interface Generator (MIG) within Vivado IDE IP Catalog. Customize the soft core memory controller for the board.
- Lab 2: MIG Design Simulation – Simulate the memory controller created in Lab 1 using the Vivado simulator.
- Lab 3: MIG Design Implementation – Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.
- Lab 4: MIG Design Debugging – Debug the memory interface design utilizing the ChipScope™ Pro tool.
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