Xilinx® Authorized Training Provider Courses > Connectivity > How to Design a Xilinx Connectivity System in 1 Day
How to Design a Xilinx Connectivity System in 1 Day

This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of transceivers, PCIe® technology, memory interfaces, and Ethernet MACs.

Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses. 
Design examples and labs are drawn from the Connectivity Targeted Reference Design (TRD). In addition, an IBERT lab is available that highlights use of the MGT.


Who Should Attend

FPGA designers and logic designers



  • Course No:  CONN13000-13-ILT
  • Course Duration:  1 Day
  • Price:  USD $700
    or 7 Xilinx Training Credits
  • Level: Connectivity 2
  • Prerequisites

    VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
    FPGA design experience or Essentials of FPGA Design course
    Basic understanding of digital and analog circuit design
    Basic understanding of high-speed serial I/O applications

  • Software Tools

    Xilinx ISE® Design Suite: Logic or System Edition 13.1

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

Do you want to receive news and schedule updates for this course? Subscribe to the Technically Speaking news email list



Transceiver Overview
Lab 1: GTP or GTXCore Generation
PCI Express Technology Overview
Lab 2: PCIe Core Generation
Memory Interfaces Overview
Lab 3: Memory Interface Design
Ethernet MAC Overview
Lab 4: TEMAC Design
AXI IP Interface Overview
Connectivity Targeted Reference Design Overview
Lab 5: IBERT Lab


Technically-Speaking, Inc. © 2014  Home | Site Map Cancellation & Privacy Policy | Terms of Use