PCIe Protocol Overview

This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.

Implementation issues are covered in the two-day Designing a LogiCORE PCI Express System course.


Who Should Attend

FPGA designers, logic designers, and anyone who needs an in-depth knowledge of the PCIe protocol



  • Course No:  PCIE 18000-13-ILT
  • Course Duration:  1 Day
  • Price:  USD $700
  • Level: Connectivity 2
  • Prerequisites


  • Software Tools

    None required

    VCD viewer optional

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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          Introduction to the PCIe Architecture
          Review of the PCIe Protocol
          Packet Formatting Details
         Lab 1: Packet Decoding
          Packet Routing
        Interrupts and Error Management



          Lab 1: Packet Decoding – This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.

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