TSI Proprietary Training Courses > HDL > Advanced VHDL Pre-Class Preparation
Advanced VHDL Pre-Class Preparation


This online course prepares students so that they receive the highest possible benefits of attending the two day Advanced Design with IEEE-1076 VHDL class.

A constant challenge for any student registering for an ‘Advanced’ course is determining if they have met the prerequisites. If not, they risk having an overall learning experience that is more frustrating than enlightening. 
This is an overall 3 hour block ( two 90 minute sessions ) of presentation and labs, along with interactive Q & A. Attendees view live software and usage demonstrations.  

Each session is strictly limited to 6 – 8 attendees.  

The agenda is derived from the classroom curriculum. However, time is spent explaining the underlying principles and applications. This additional insight prepares each student for the full and rich learning experience of the two day classroom session.

Who Should Attend

Engineers already planning to attend, or considering the two day Advanced VHDL Class.



  • Course No:  AdvVHDL Pre-Class Prep
  • Course Duration:  2 ( 90 Minute ) Sessions
  • Price:  USD $100
    or 1 Xilinx Training Credits
  • Level: HDL 3
  • Prerequisites

    Completion the 3 day Designing with VHDL Course
    ( or equivalent working IEEE-1076 VHDL knowledge )

  • Software Tools

    ISE 13.1

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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A derivative of the 2 day Advanced VHDL Class curriculum, as shown here:

?          Advanced Simulation Concepts
?          VHDL Subprograms
?          Lab 1: Write Subprogram for Testbench
?          Self-testing Techbenches
?          Advanced Text I/O Usage
?          Lab 2: Read & Write Simulation Data
?          User Defined Log files
?          Lab3: Automated Comparison
Day 2
?          Access Data-Types
?          Creating Link List
?          Lab 4: Use Access Data-types
?          FSM Design and Optimization
?          Lab 5: Create and Simulate FSM
?          Handling Non-Integers
?          Lab 6: Implementing Fixed and Floating Point Numbers


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