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FPGA Design Fundamentals

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Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.

This course covers ISE software features such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.

For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.

Who Should Attend

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Recommended RELs

At-A-Glance	Schedule
Course No: XAP1_FPGA13000 Course Duration: 8:00 HR Price: USD $700 or 7 Xilinx Training Credits Level: Intermediate Prerequisites Working HDL knowledge (VHDL or Verilog) Digital design experience Software Tools Xilinx ISE Design Suite: Logic or System Edition 13.3	Nothing currently scheduled. Please contact us for customized classes. Tel: 303.444.7884 • Fax: 866.402.0763

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COURSE OUTLINE

Course Agenda

Basic FPGA Architecture

Xilinx Tool Flow

Lab 1: Xilinx Tool Flow

Reading Reports

Lab 2: Clocking Wizard and Pin Assignment

Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool

Global Timing Constraints

Lab 4: Global Timing Constraints

Synchronous Design Techniques

Course Summary

LAB DESCRIPTION

Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to the evaluation board.

Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.

Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.

Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.