Review of FPGA Design Fundamentals
Designing with FPGA Resources
Lab 1: Designing With FPGA Resources
FPGA Design Techniques
Achieving Timing Closure
Lab 2: Review of Global Timing Constraints
Path-Specific Timing Constraints, Part 1
Path-Specific Timing Constraints, Part 2
Lab 3: Achieving Timing Closure
Advanced I/O Timing Constraints
Lab 4: Source/System Synchronous Constraints
Lab 1: Designing with FPGA Resources – Create clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and implement the design.
Lab 2: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
Lab 3: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.
Lab 4: Use post P&R timing report files to align clock and data