Advanced Timing Constraints




Who Should Attend

 FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools, or those having attended XAP Session 1




  • Course No:  XAP2_FPGA23000
  • Course Duration:  8:00 HR
  • Price:  USD $700
    or 7 Xilinx Training Credits
  • Level: Advanced
  • Prerequisites

     XAP Session 1

    Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
    Intermediate HDL knowledge (VHDL or Verilog)
    Solid digital design background
  • Software Tools

     ISE Design Suite: Logic or System Edition 13.3

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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 Review of FPGA Design Fundamentals

Designing with FPGA Resources
Clocking Resources
Lab 1: Designing With FPGA Resources
FPGA Design Techniques
Achieving Timing Closure
Lab 2: Review of Global Timing Constraints
Path-Specific Timing Constraints, Part 1
Path-Specific Timing Constraints, Part 2
Lab 3: Achieving Timing Closure
Advanced I/O Timing Constraints
Lab 4: Source/System Synchronous Constraints


 Lab 1: Designing with FPGA Resources – Create clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and implement the design.
Lab 2: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
Lab 3: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.
Lab 4: Use post P&R timing report files to align clock and data

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