Optimal HDL Coding

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MORE INFO ON XAP PRICES/PACKAGES/CURRICULUM

 

 Attending the Optimal HDL Coding class will help you bridge the gap between your high-level RTL source code and the FPGA device specific resources. As Xilinx devices becomes more complex, with more dedicated blocks, high-level clocking resources and special functions, the challenge of optimizing your VHDL or Verilog source code is greater. Certain resources may not be inferred. Meanwhile others require specific coding, and yet others require that you set specific synthesis options. This one day XAP session focuses on this unique issue for both VHDL and Verilog users.

  



Who Should Attend

 FPGA designers with a working knowledge of HDL and some experience with the Xilinx ISE® software tools.



At-A-Glance

Schedule

  • Course No:  XAP3_HDL_OPT
  • Course Duration:  8:00 HR
  • Price:  USD $700
    or 7 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites

     XAP Session 1 or Session 2

    Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
    Intermediate HDL knowledge (VHDL or Verilog)
    Solid digital design background
  • Software Tools

     ISE Design Suite: Logic or System Edition 13.3

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

 Review of Advanced Timing Constraints (XAP 2)

HDL Design Flow for FPGAs
Xilinx FPGA resources and building blocks
Lab 1: Using CoreGen versus infererence
Specific HDL coding guidelines
Using Timing Constraints to drive Synthesis
Lab 2: Compile with Timing Constraints
Best HDL practices and Techniques
XST and Syplify Pro menus and options
Lab 3: Explore compiler options, impact on results

LAB DESCRIPTION

Lab 1: Use CoreGen to create resources, compare area and speed to results using inference for same functional block.
Lab 2: Use Timing Constraints to drive synthesis, observe and measure impact on synthesis results.
Lab 3: Understand and apply various synthesis options that directly affect chip level resource utilization and mapping.


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