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Designing with PlanAhead Part 1

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Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software. Topics include: a product overview, synthesis and project tips, I/O pin assignment, design analysis,Pblocks, creating a floorplan, improving performance.

Who Should Attend

FPGA designers, system architects, and system engineers who are interested in analyzing and driving the physical implementation of their designs to maximize performance and capacity.

At-A-Glance

Schedule

Course No: XAP4_PA1
Course Duration: 8:00 HR
Price: USD $700
or 7 Xilinx Training Credits
Level: Intermediate
Prerequisites

xAP1 & XAP2, or XAP2 & XAP3

Essentials of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE® software flow

Designing for Performance recommended? XAP1 & XAP2, or XAP2 & XAP3

Essentials of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE® software flow

Designing for Performance recommended
Software Tools
Xilinx ISE Design Suite: Logic or System Edition 13.1

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763

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COURSE OUTLINE

PlanAhead Tool Features Overview

Lab 1: Getting Started with the PlanAhead Tool

I/O Pin and Clock Planning

Lab 2: Assigning I/O Pins

RTL Development and Analysis

Lab 3: RTL Development and Analysis

Implementing a Design Lab 4: Implementing with the PlanAhead Tool

LAB DESCRIPTION

Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.

Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.

Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.

Lab 3: RTL Development and Analysis – Provides an overview of the RTL development and analysis environment. You will analyze the RTL logic hierarchy, RTL schematic, RTL resource estimations and run RTL Design Rule Check (DRCs).

Lab 4: Implementing with the PlanAhead Tool – Illustrates a walkthrough of the front-to-back, RTL-to-bitstream design flow. You will run synthesis, import synthesis results, run implementation, and import and analyze the implementation.