Advanced FPGA Implementation Options & Chipscope Pro
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Advanced FPGA Implementation and ChipScope Pro tackle the most sophisticated aspects of the ISE® design suite and Xilinx hardware. The lecture material in this course covers the ISE tools and the 7 series FPGAs. As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug. Hands-on labs demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.
Who Should Attend
Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity as well as designers who want to minimize verification and debug time
- Course Duration: 8:00 HR
- Price: USD $700
XAP2 & XAP3 & XAP4, or XAP3 & XAP4 & XAP5
Essentials of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE® software flow
Designing for Performance recommended
Xilinx ISE Design Suite: Logic or System Edition 11.1
Nothing currently scheduled.
Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763
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Lab 1: Tcl Scripting
FPGA Editor: Viewing and Editing a Routed Design
Lab 2: Advanced FPGA Editor
How the ChipScope Pro Tool Works
Inserting the Cores – Inserter Flows: Core Inserter and the PlanAhead Software
Labs 3 and 4: Using the Inserter Tool from Project Navigator and Using the Inserter Tool from the PlanAhead software
Instantiating the Cores – The CORE Generator Tool Flow
Lab 5: Using the CORE Generator Tool from Project Navigator
Triggering and Storage
Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.
Lab 1: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
Lab 2: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.
Labs 3 and 4: Using the Inserter Tool from Project Navigator (Lab 3) and Using the Inserter Tool from the PlanAhead Software (Lab 4) – Insert an ICON and ILA cores into an existing netlist and debug a common problem.
Lab 5: Using the CORE Generator Tool from Project Navigator – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool.