Xilinx® Authorized Training Provider Courses > XAP Academy > How to Design Xilinx Digital Signal Processing System 1day
How to Design Xilinx Digital Signal Processing System 1day

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The workshop introduces you to fundamental DSP concepts, algorithms, and techniques for implementation in Xilinx FPGAs. Design examples and labs are drawn from several common applications spaces, including wireless communications, video, and imaging.
Only essential theory is introduced in order to lay a foundation for the material and topics covered in this workshop, which complements more detailed training found in subsequent Xilinx courses.

 

 

 

 



Who Should Attend

 FPGA designers and logic designers



At-A-Glance

Schedule

  • Course No:  XAP7_DSP
  • Course Duration:  8:00 HR
  • Price:  USD $700
    or 7 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites

    VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course

    FPGA design experience or Essentials of FPGA Design course
    Fundamental understanding of digital signal processing theory
    Fundamental understanding of FIR filter and FFT theory
    Very basic understanding of FPGA architecture
  • Software Tools

     Xilinx ISE® Design Suite: DSP or System Edition 13.1

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

 Workshop Overview

Virtex-6 and Spartan-6 FPGA Architecture
DSP Essentials
Lab 1: Introduction to System Generator
System Generator Design Flow
Lab 2: Filter and FFT Design
FFT Basics
Lab 3: DSP Targeted Design Platform
Video and Imaging IP
Lab 4: Video Processing and Shared Memory

LAB DESCRIPTION

 Lab 1: Introduction to System Generator – In this lab, you will create a simple modulation system that will consist of a Direct Digital Synthesizer (DDS) module for generating a sine wave and a multiplier created using a DSP48.

Lab 2: Filter and FFT Design – In this lab, two important blocks are examined: the FIR Compile and FFT. The design includes serialization of parallel data and up sampling and filtering the data. The lab also presents how to use and configure the FFT block.
Lab 3: DSP Targeted Design Platform – This lab illustrates a WCDMA single carrier DUC / DDC design based on a reference design in Application Note XAPP1018. Hardware co-simulation is also performed.
Lab 4: Video Processing and Shared Memory – This lab demonstrates using DSP System Generator in a video processing design as well as utilizing hardware co-simulation with shared memory.

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