Designing with Verilog

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience.
Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

COURSE DESCRIPTION



Who Should Attend

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs



At-A-Glance

Schedule

  • Course No:  LANG12000-ILT
  • Course Duration:  3 Days
  • Price:  USD $1,800
    or 18 Xilinx Training Credits
  • Level: FPGA 1
  • Prerequisites

    Basic digital design knowledge

  • Software Tools

             Vivado System Edition 2014.1

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

Day 1

  •           Hardware Modeling Overview
  •           Verilog Language Concepts
  •           Modules and Ports
  •        Demo: Multiplexer
  •           Lab 1: Building Hierarch
  •           Introduction to Testbenches
  •           Lab 2: Verilog Simulation and RTL Verification

Day 2

  •           Verilog Operators and Expressions
  •           Continuous Assign Statements
  •           Lab 3: Memory
  •           Verilog Procedural Statements
  •           Lab 4: Clock Divider and Address Counter
  •           Controlled Operation Statements
  •           Lab 5: n-bit Binary Counter and RTL Verification

Day 3

  •           Verilog Tasks and Functions
  •           Advanced Language Concepts
  •           Finite State Machines
  •           Lab 6: Finite State Machines
  •           Targeting Xilinx FPGAs
  •           Lab 7: Implement and Download
  •           Advanced Verilog Testbenches
  •           Lab 8: Using Verilog File I/O

LAB DESCRIPTION

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.


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