How to Design a Xilinx Connectivity System in 1 day (XAP)
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MORE INFO ON XAP PRICES/PACKAGES/CURRICULUM
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This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of transceivers, PCIe® technology, memory interfaces, and Ethernet MACs.
Who Should Attend
FPGA designers and logic designers
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At-A-Glance |
Schedule |
- Course
No: XAP9_CONN
- Course Duration: 8:00 HR
- Price: USD $700
or 7 Xilinx
Training Credits
- Level:
Intermediate
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Prerequisites
VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
FPGA design experience or Essentials of FPGA Design course
Basic understanding of digital and analog circuit design
Basic understanding of high-speed serial I/O applications
- Software
Tools
Xilinx ISE® Design Suite: Logic or System Edition 13.1
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Nothing currently scheduled.
Please contact us for customized classes.
Tel: 303.444.7884 • Fax: 866.402.0763
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COURSE OUTLINE
Introduction
Transceiver Overview
Lab 1: GTP or GTX Core Generation
PCI Express Technology Overview
Lab 2: PCIe Core Generation Memory Interfaces Overview
Lab 3: Memory Interface Design
Ethernet MAC Overview
Lab 4: TEMAC Design
AXI IP Interface Overview
Connectivity Targeted Reference Design Overview
Lab 5: IBERT Lab
LAB DESCRIPTION
Lab 1: GTP or GTX Core Generation – Use the GTP/GTX Transceiver Wizard to create the transceiver core.
Lab 2: PCIe Core Generation – Introduces the CORE Generator™ interface for generating the PCIe core for the Spartan-6 or Virtex-6 FPGA.
Lab 3: Memory Interface Design – Create a DDR3 memory controller with the Memory Interface Generator (MIG) CORE Generator interface that will be used in a pre-written design. Download onto the development board to verify functionality.
Lab 4: TEMAC Design – Use the CORE Generator interface to generate a Tri-Mode Ethernet MAC core.
Lab 5: IBERT Lab – Use the ChipScope™ Pro tool IBERT design to verify a GTP link on the Spartan-6 SP605 board or a GTX link on the Virtex-6 ML605 board. |
