Xilinx® Authorized Training Provider Courses > Connectivity > How to Design a Xilinx Connectivity System in 1 day (XAP)
How to Design a Xilinx Connectivity System in 1 day (XAP)

 DOWNLOAD COURSE DESCRIPTION

This workshop introduces you to fundamental connectivity concepts and techniques for implementation in Xilinx FPGAs. The focus is on fundamental aspects of transceivers, PCIe® technology, memory interfaces, and Ethernet MACs.

 

 

 

 

 



Who Should Attend

 FPGA designers and logic designers



At-A-Glance

Schedule

  • Course No:  CONN13000-ILT
  • Course Duration:  8:00 HR
  • Price:  USD $700
    or 7 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites

     VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course

    FPGA design experience or Essentials of FPGA Design course
    Basic understanding of digital and analog circuit design
    Basic understanding of high-speed serial I/O applications
  • Software Tools

     Xilinx ISE® Design Suite: Logic or System Edition 2013.2

Nothing currently scheduled.

Please contact us for customized classes.
Tel: 714.227.8666 • Fax: 866.402.0763

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COURSE OUTLINE

 

          Introduction

          Transceiver Overview

          Lab 1: Transceiver Design

          PCI Express Technology Overview

          Lab 2: PCIe Design

          Memory Interfaces Overview

          Lab 3: MIG Design

          Ethernet MAC Overview

          Lab 4: TEMAC Design

          AXI and  IP Interface Overview

          Connectivity Applications

          Lab 6: IBERT Lab

LAB DESCRIPTION

 

          Lab 1: Transceiver Design – Use the 7 Series FPGAs Transceiver Wizard to create a GTX transceiver IP. Optionally, download onto the development board to verify functionality.

          Lab 2: PCIe Design – Introduces the Vivado IP catalog interface for generating the PCIe block design for a Kintex-7 FPGA application. Optionally, verify functionality in a real system.

          Lab 3: Memory Interface Design – Create a DDR3 memory controller with the 7 series MIG within the Vivado IP catalog that will be used in a pre-written design. Optionally, download onto the development board to verify functionality.

          Lab 4: TEMAC Design – Use the Tri Mode Ethernet MAC IP within the Vivado IP catalog to generate an EMAC application. Optionally, verify functionality in a real system.

          Lab 6: IBERT Lab – Use the 7 series FPGAs IBERT design to verify a GTX link on the development board.


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