This normally 2-day class will delivered in 4 half-day sessions online.
This course provides a thorough introduction to the Vivado® High-Level Synthesis (HLS) tool.
The focus is on:
What's New for 2020.1
* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will have the necessary skills to:
Day 1
Overview of the High-level Synthesis (HLS), Vivado HLS tool flow, and the verification advantage. {Lecture}
Explore the basics of high-level synthesis and the Vivado HLS tool. {Lecture, Demo, Lab}
Explore different optimization techniques that can improve the design performance. {Lecture}
Describes the Vivado HLS tool flow in command prompt mode. {Lecture, Lab}
Introduces the methodology guidelines covered in this course and the HLS UltraFast Design Methodology steps. {Lecture}
Explains interfaces such as block-level and port-level protocols abstracted by the Vivado HLS tool from the C design. {Lecture}
Explains the different types of block-level protocols abstracted by the Vivado HLS tool. {Lecture, Lab}
Describes the port-level interface protocols abstracted by the Vivado HLS tool from the C design. {Lecture, Demo, Lab}
Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vivado HLS tool. {Lecture, Demo}
Describes the memory interface port-level protocols (such as block RAM, FIFO) abstracted by the Vivado HLS tool from the C design. {Lecture, Lab}
Explains the bus protocol supported by the Vivado HLS tool. {Lecture}
Describes the PIPELINE directive for improving the throughput of a design. {Lecture, Demo, Lab}
Day 2
Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible. {Lecture, Lab}
Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance. {Lecture, Demo, Lab}
Learn how to use DATA_PACK and DEPENDENCE directives to overcome the limitations caused by structures and loops in the design. {Lecture}
Describes the default behavior of the Vivado HLS tool on latency and throughput. {Lecture}
Describes how to optimize the C design to improve latency. {Lecture}
Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization. {Lecture, Lab}
Describes the traditional RTL flow versus the Vivado HLx design flow. {Lecture, Lab}
Describes the Vivado HLS tool support for the C/C++ languages, as well as arbitrary precision data types. {Lecture, Lab}
Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class. {Lecture}
Explains the use of pointers in the design and workarounds for some of the limitations. {Lecture}