This 1 and 1/2-Day course focuses solely on the topic and challenge of Xilinx FPGA Timing Closure using the Vivado Design Suite. The class covers all XDC Timing Constraints and then discusses strategies such as Baselining, using phy_opt_design and handling global resets. This single class bridges the gap between HDL coding styles and FPGA results. It also shows how to use various report commands to better analyze and correct critical timing paths.
This course also covers UG1292 UltraFast Design Methodology Timing Closure Quick Reference.
Level – FPGA 3
Course Duration – 1 day
Price – $1200 USD or 12 TCs ( Training Credits)
Printed Materials – BW: included, Full Color: Add $95
Course Part Number – FPGA-VTC_FULL-ILT
Who Should Attend? – FPGA Designers who want to ensure they have properly constrained the design while maximizing the tool effort. Designers wanting detailed critical path analysis and resolution.
▪ Basic knowledge of the VHDL or Verilog language
▪ Digital design knowledge
▪ Basic FPGA Architecture
▪ Basic Vivado DS Design Flows (Project/ Non-Project)
Recommended Recorded Videos
▪ Basic FPGA Architecture: Slice and I/O Resources*
▪ Basic FPGA Architecture: Memory and Clocking Resources*
▪ Vivado Design or System Edition 2017.3 to 2020.x
▪ Architecture: UltraScale™ and 7 series FPGAs**
After completing this comprehensive training, you will have the necessary skills to: