Product Accelerating Applications with the VITIS Unified Software Environment | Online & San Diego, CA Accelerating Applications with the VITIS Unified Software Environment | Online 2020.2 ( 1/2 Day Format) Advanced VHDL | Online AI Engine: Step-By-Step Programming Building Winning Business Relationships Business Etiquette C-based Design: High-Level Synthesis with the Vivado HLx Tool | Online - Vivado 2020.2) Color Printed Xilinx Course Materials (2-Day) Communication Essentials for Leaders Communication Essentials for Leaders | San Jose CA Conducting Dynamic Webinar and Remote Presentations Conducting Dynamic Webinar and Remote Presentations | San Jose CA Cross Cultural Communication Cross Cultural Communication | Online Cross Cultural Communication | San Jose, CA Custom ASML: Versal Adaptive SoC Programming Bootcamp Custom VHDL & Vivado for NGC Custom VHDL & Vivado for NGC T2 Deconstructing the Technical Presentation Delivering Effective Presentations (DEP) – Advanced Workshop Delivering Effective Presentations (DEP) – Advanced Workshop | San Jose, CA Delivering Effective Presentations (DEP) – Introductory Workshop Delivering Effective Presentations - Leadership Designing an Integrated PCI Express System | Online & Onsite - San Diego CA Designing FPGAs Using the Vivado Design Suite 1 | Online Designing FPGAs Using the Vivado Design Suite 2 | Online (Vivado 2022.1) Designing FPGAs Using the Vivado Design Suite 3 | Online (Vivado 2020.2) Designing FPGAs Using the Vivado Design Suite 4 | Online (Vivado 2020.2) Designing w/ VERSAL ACAP; Architecture and Design Methodology Designing w/ VERSAL AI Engine (Level 1) Designing with IEEE-1076 VHDL and Xilinx Vivado DS (2020.x) - ONLINE Designing with the IP Integrator Tool (2022.1) | 1/2 day format Designing with the Versal ACAP Network on Chip (NoC) Designing with the Versal ACAP: Architecture and Methodology Designing with the Versal ACAP: Power and Board Design Designing with VHDL | Online Designing with Xilinx Serial Transceivers Designing with Xilinx Serial Transceivers Developing AI Inference Solutions with the Vitis AI Platform Developing AI Inference Solutions with the Vitis AI Platform| 2020.x DSP Design Using System Generator & Model Composer | Online DSP Primer DSP Using System Generator, Model Composer and FPGA Implementation Techniques | Online Dynamic Function Exchange (DFX) Embedded Design with PetaLinux Tools | Online Embedded Systems Design Hardware | Vivado / Vitis 2020.x Embedded Systems Software Design I Online ( Vivado & Vitis 2019.1) Essential DSP Implementation Techniques Essentials of Conflict Management and Mediation HDL and FPGA Design High-Level Synthesis with Vitis 2022.2 How to Design a High-Speed Memory Interface KRIA Vision Based Apps w/KV260 Managing Change Migrating to the Vitis IDE Software Development Workshop - 2020.1 NAWCWD Xilinx Versal & Related Non‐Verbal Communication: The Influence of Body Language One-on-One (1:1) Executive Coaching – Presentations Powerful Persuasion and Influence Techniques Powerful Persuasion and Influence Techniques | Las Vegas, NV Powerful Persuasion and Influence Techniques | San Jose, CA PowerPoint - Mastering Design and Impact QTI Onsite Versal Programming Bootcamp Skillfully Managing Q&A Sessions Skillfully Managing Q&A Sessions | San Jose CA Successful Team Building and Collaboration Methods SW Regional Versal Adaptive SoC (Per Day)) System Verilog for MOOG Timing Closure Techniques for Vivado DS | ABQ & Online Timing Closure Techniques for Vivado DS | LAX & Online Timing Closure Techniques for Vivado DS | Online (1/2 day format) UltraFast Design Methodology | Vivado 2020.1 UltraScale and UltraScale+ Architectures Updated coding requirements for Versal AI Engines Using DSP Libraries for Versal AI Engine Programming Using Model Composer for AI Engine Development Using VCK190 for FIR Design and Model Composer for Verification Versal : PCIe Systems Versal ACAP: AI Engines - Demystifying and Programming Versal Adaptive SoC Programming Boot-Camp (Albuquerque, NM)) Versal Adaptive SoC Programming Boot-Camp (Albuquerque, NM)) Versal Adaptive SoC Programming Boot-Camp (LAX) Versal Adaptive SoC Programming Boot-Camp (ONLINE)) Versal Adaptive SoC Programming Boot-Camp (Orange County, CA) Versal Adaptive SoC Programming Boot-Camp (Phoenix, AZ) Versal Adaptive SoC Programming Boot-Camp (Portland, OR) Versal Adaptive SoC Programming Boot-Camp (San Diego, CA) Versal Adaptive SoC Programming Boot-Camp (Seattle, WA)) Versal Adaptive SoC Programming Boot-Camp (Woodland Hills, CA) Versal Adaptive SoC Programming Bootcamp (San Jose, CA) Vitis and PetaLinux Vitis and PetaLinux - Creating an Extensible Platform Vitis for Versal ACAP Vitis Model Composer: A MATLAB / Simulink Product Vivado Advanced FPGA Design Vivado FPGA Design Essentials What is HLS, and Why Does it Matter? Women in Technology Seminar Xilinx Partial Reconfiguration Tools and Techniques 2020.1 You Can't Lie To Me You Can't Lie To Me | Las Vegas, NV Zynq All Programmable SoC System Architecture Zynq UltraScale+ RFSoC Zynq UltraScale+MPSoC – Combined Course for Software Designer/System Architect/Hardware Designer | Online