High Level Synthesis (HLS) is a game-changer!  The ability to use a few snippets of C\C++ code to rapidly create, verify and optimize IP has given early adapters a distinct productivity
advantage.

HLS is here to stay, and it keeps getting better!  It’s utilized for both ASICs and FPGAs.

To be certain, HLS does not replace traditional VHDL or Verilog coding! Rather, it enhances it by allowing some complex IP to be modeled at a higher level  of abstraction.  Think data-flow
oriented processing blocks.  Think DSP operations and streaming data.  Think computationally intensive C\C++ functions that benefit from hardware acceleration.

That IP is still integrated into higher level RTL code, either directly or by using Vivado IPI.