Timing Closure Techniques for Vivado DS | Online (1/2 day format)

Technically Speaking International, INC

Timing Closure Techniques for Vivado DS | Online (1/2 day format)

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$ 1200.00



Course Description

This 1 and 1/2-Day course focuses solely on the topic and challenge of Xilinx FPGA Timing Closure using the Vivado Design Suite.  The class covers all XDC Timing Constraints and then discusses strategies such as Baselining, using phy_opt_design and handling global resets.  This single class bridges the gap between HDL coding styles and FPGA results.  It also shows how to use various report commands to better analyze and correct critical timing paths.

This course also covers UG1292 UltraFast Design Methodology Timing Closure Quick Reference.


Level – FPGA 3

Course Duration – 1 day

Price – $1200 USD or  12 TCs ( Training Credits)

Printed Materials – BW: included, Full Color: Add $95

Course Part Number – FPGA-VTC_FULL-ILT

Who Should Attend? –  FPGA Designers who want to ensure they have properly constrained the design while maximizing the tool effort. Designers wanting detailed critical path analysis and resolution.


▪          Basic knowledge of the VHDL or Verilog language

▪          Digital design knowledge

▪          Basic FPGA Architecture

▪          Basic Vivado DS Design Flows (Project/ Non-Project)

Recommended Recorded Videos

▪          Basic FPGA Architecture: Slice and I/O Resources*

▪          Basic FPGA Architecture: Memory and Clocking Resources*

Software Tools

▪          Vivado Design or System Edition 2017.3 to 2020.x


▪          Architecture: UltraScale™ and 7 series FPGAs**



After completing this comprehensive training, you will have the necessary skills to:

  • Understand the Vivado STA estimation model
  • Enter primary clock constraints as needed
  • Add generated and virtual clocks were appropriate
  • Determine if constraints are reasonable
  • Apply source-synchronous I/O interface constraints
  • Fully and properly constrain multi-cycle paths
  • Handle path exceptions,false paths, min/max delays
  • Use case analysis
  • Describe the Xilinx recommended "baselining" process
  • Properly constrain synchronization circuits
  • Handling clock domain crossing (CDC)
  • Determine when Floorplanning is beneficial
  • Access key reports for design QoR
  • Preserve existing timing using incremental design techniques
  • Leverage benefits of incremental synthesis
  • Read STA report for key insights and details

Course Outline

Day 1

  • Timing Closure Overview
  • HDL Coding Techniques
  • Vivado STA Overview
  • Introduction to Clock and Generated Clock Constraints
  • I/O Constraints and Virtual Clocks
  • Timing Constraints Wizard (Demo)
  • Introduction to Vivado Reports
  • Setup and Hold Timing Analysis
  • Baselining Techniques
  • Handling Clock-Domain-Crossings (CDC)
  • Detailed Critical Path Analysis
  • Handling Resets
  • Case Analysis


Day 2

  • Design Preservation (Demo) / Incremental Design Flow (Demo)
  • Floorplanning Overview
  • IP Specific XDC
  • Detailed Timing Report Analysis (case study)
  • Generating Custom Timing Report
  • Using phys_opt_design




Topic Descriptions

  • Good HDL coding is the first step to timing closure. Use of resets, conditional statements, inference versus instantiating hard IP.
  • How STA works with Vivado, using fast and slow process corners for analysis, clock pessimism, MMCM impact.
  • Creating primary clock constraints, matching MMCM specification
  • Constraining generated clocks, either user-defined or MMCM/HSSIO
  • System Synchronous input/ouput constraints and virtual clocks
  • Source Synchronous interface requirements and syntax
  • Timing Constraint Wizard for entry and verifying existing constraints
  • Using key Vivado reports for timing analysis and design QoR
  • Properly constraining and analyzing CDCs .
  • Detailed critical path analysis, what to look for to pinpoint cause of timing failure, apply appropriate correction.
  • Constraint Baselining Techniques
  • Recommendations for reset signal, global and local
  • Using case analysis to streamline timing analysis when appropriate
  • Maintaining existing timing results as design is modified
  • Determine circumstances where floorplanning is useful or potentially counter-productive
  • Managing IP specific XDC timing constraints